Circuitry for adjusting luminance of a display device is provided. The circuitry includes a non-volatile memory array having a plurality memory cells configured to store luminance data of the display device, and a luminance adjusting circuit configured to receive image data to be displayed on the display device. The luminance adjusting circuit is coupled directly to the non-volatile memory array to receive the luminance data of the display device from the non-volatile memory array and adjust the image data based on the luminance data of the display device.

An integrated circuit with data communication stability in a noise environment includes at least one input section through which a signal is input from a user, at least one output section through which information is output in a predetermined form, and a microcontroller unit (MCU), independently of the microcontroller unit (MCU), and communicates with the microcontroller unit to control, on the basis of the input signal generated from the at least one input section, output driving of the output section corresponding thereto, the integrated circuit including: a serial interface that includes an Rx pin for receiving a data signal from the microcontroller unit by forming a signal reception line with respect to the microcontroller unit and a Tx pin for transmitting a data signal to the microcontroller unit by forming a signal transmission line with respect to the microcontroller unit.

A receiver of a display driver and an operating method of the receiver of the display driver are provided. The receiver of the display driver includes an input interface, an operational amplifier and a bias current control circuit. The input interface receives image data. The operational amplifier is coupled to the input interface and includes a bias current circuit. The bias current control circuit adjusts a bias current of the bias current circuit according to a data rate of the image data. The operating method is adapted to the receiver of the display driver.

Embodiments of the disclosure relate to a control circuit, a display device, and a method for driving a main processor. Specifically, there may be provided a control circuit, a display device, and a method for driving a main processor which may reduce power consumption in the transmission/reception circuit connected with the interface by powering off at least one of the source transmission/reception circuit or sink transmission/reception circuit electrically connected with the auxiliary channel AUX during at least a partial period of the vertical blank period.

Technology for a display source controller is described. The display source controller can receive display pixel data from a display source. The display source controller can convert the display pixel data to display symbol data that includes a plurality of 32-bit double words (DWords). The display source controller can divide the display symbol data that includes the plurality of 32-bit DWords for a number of unidirectional serial data channels. The display source controller can process, for each unidirectional serial data channel, the display symbol data at a 32-bit DWord granularity level. The display source controller can send the display symbol data for each of the unidirectional serial data channels over a physical serial link to a display panel.

Active control of LEDs, LED packages, and related LED displays by way of pulse wide modulation (PWM) is disclosed. Effective PWM frequencies for LEDs are increased by segmenting duty cycles in which LEDs are electrically activated within individual PWM periods. Segmented duty cycles may be provided by transforming or re-ordering a sequence in which control signals are provided to LEDs. As such, LEDs may be electrically activated and deactivated multiple times within each PWM period. Active electrical elements that are incorporated into one or more LED packages of an LED display may be capable of segmenting the duty cycle within each LED package. Active electrical elements may also be capable of receiving reset signals from a data stream to either initiate a reset action or pass the reset signals along to other active electrical elements of a display.

It is an object to realize a correcting process for correcting a defective image in a region of interest (ROI) that is a partial region segmented from a captured image. A transmitting apparatus includes a controlling section that controls the holding of defect correcting information for use in correcting a defect in an image included in a ROI and a transmitting section that sends out image data of the image included in the ROI as payload data and sends out ROI information as embedded data.

A phase calibration method includes sweeping phase codes applicable to a serial clock signal, identifying a first, a second, a third, and a fourth phase code, wherein the first phase code causes zero plus a first threshold number of bits extracted from the serial data signal to be a particular value, wherein the second phase code causes all minus a second threshold number of bits extracted from the serial data signal to be the particular value, wherein the third phase code causes all minus a third threshold number of bits extracted from the serial data signal to be the particular value, wherein the fourth phase code causes zero plus a fourth threshold number of bits extracted from the serial data signal to be the particular value, determining an average phase code based on the identified phase codes.

Disclosed herein is a data interface device of a display apparatus including a timing controller, encoding clock-embedded image data corresponding to a logic high period of a data enable signal and clock-embedded blank data corresponding to a logic low period of the data enable signal and transferring an encoded data transfer packet to a transfer line, and a source integrated circuit generating an internal clock based on the encoded data transfer packet received through the transfer line and selectively decoding the clock-embedded image data based on the internal clock, wherein a transition pattern of the clock-embedded blank data differs in a plurality of transfer lines.

A display control integrated circuit (IC) applicable to performing multi-display processing in a display device includes multiple sub-circuits such as a Multi-Stream Transport (MST) stream splitting module, multiple video format conversion circuits, a multiplexer and a video combination module for generating a combined picture for being displayed. The display control IC may utilize at least one additional data path coupled to at least one predetermined sub-circuit among the multiple sub-circuits to obtain at least one signal, and output any signal of the at least one signal through a video output terminal of the display control IC and a video output port of the display device to be a video output signal for further use, where the at least one predetermined sub-circuit include at least one of the MST stream splitting module and the multiplexer.