Embodiments of the disclosure relate to a receiving card, which includes: a circuit board and a programmable logic device, a memory device, a plug-in component, a physical layer transceiver group and a plurality of Ethernet interfaces arranged on the circuit board. The memory device and the plug-in component are electrically connected with the programmable logic device; the plurality of Ethernet interfaces are respectively and electrically connected with a plurality of SerDes channels configured by the programmable logic device through the physical layer transceiver group; each of the plurality of SerDes channels includes two pairs of differential signal lines, and one of the two pairs of differential signal lines is used for transmitting data and the other pair of differential signal lines is used for receiving data.

A display panel and a driving method thereof are provided, including a time schedule controller and at least one driver integrated circuit (driver IC). Pulse width modulation (PCM) data between the time schedule controller and the driver IC is transmitted in a decoded manner, and pulse amplitude modulation (PAM) data is transmitted in an undecoded manner, reducing a transmission rate between the time schedule controller and the driver IC, and thereby reducing or eliminating risks of electromagnetic interference (EMI). Furthermore, using this transmission method can reduce the number of latches used in the driver IC.

A display control system includes a plurality of driver circuits connected in series. A driver circuit among the plurality of driver circuits includes a receiver, a duty cycle correction circuit and a transmitter. The receiver is configured to receive a first signal from a previous driver circuit among the plurality of driver circuits. The duty cycle correction circuit, coupled to the receiver, is configured to adjust a duty cycle of the first signal to generate a second signal. The transmitter, coupled to the duty cycle correction circuit, is configured to transmit the second signal to a next driver circuit among the plurality of driver circuits.

A display device including: a display panel including a plurality of pixels; a data driver configured to provide data voltages to the plurality of pixels; and a controller configured to control the data driver, to detect a same data region of the display panel when first image data in a current frame period is the same as second image data in a previous frame period, and not to transfer the first image data to the data driver in the current frame period.

A video display includes a display panel with gate drivers and source drivers. Each of said the source drivers is arranged to receive a discrete-time continuous-amplitude signal representing a video stream over a transmission medium and to decode the signal using demodulation to produce a plurality of samples for output on outputs of the source drivers. At least one of the source drivers is arranged to extract a gate driver timing control signal from the signal and to output the gate driver control signal to the gate drivers in order to synchronize the gate drivers with outputs of the source drives, whereby the video stream is displayed on the display panel of the display unit.

The preset disclosure provides a data burning method and a data burning device. The data burning method comprises receiving a differential signal data packet, which is transmitted by a signal generator, by a driver IC through a differential signal interface, the differential signal data packet including grayscale data; parsing the differential signal data packet by the driver IC to obtain the grayscale data; and burning the grayscale data to a memory by the driver IC.

A method of handling signal transmission applicable to a display system includes a plurality of steps. The steps include transmitting a reset signal embedded in a first data signal to each of at least one source driver via a first data channel, generating a first control signal for setting the at least one source driver, and transmitting the first control signal embedded in a second data signal to each of the at least one source driver via a second data channel when the reset signal is transmitted via the first data channel.

A circuit device 100 includes an interface circuit 160 that receives image data and information for image check and a processing circuit 105 that performs image check processing. The information for image check includes information for designating an image check method for a region to be subjected to image check and position information of the region to be subjected to image check. The processing circuit 105 performs the image check processing on the image data of the region to be subjected to image check specified by the position information, using the image check method designated by the designation information.

An interface circuit comprises a timing signal generating unit that generates a timing signal indicating a timing to switch between a data input period and a non-input period, a plurality of driver error detection circuits that detects an error in source drivers, a selector circuit that selects one of the driver error detection circuits in the non-input period and that outputs a driver error detection signal indicating an error detection result, an input error detection circuit that detects an input error of a data signal and outputs an input error detection signal indicating the result, an OR circuit that outputs an OR of the driver error detection signal and the input error detection signal, and a signal output unit connected to an output part of the OR circuit.

A display device includes a display panel including pixels, and data lines and gate lines connected to the pixels, a timing controller configured to output source driving bit information and gate driving bit information through an intra-interface signal, a source driver configured to generate data driving signal based on the source driving bit information and to supply the data driving signal to the data lines, and a gate driver configured to generate a gate driving signal based on the gate driving bit information and to supply the gate driving signal to the gate lines, wherein the intra-interface signal is configured with predetermined data transmission units and includes both the source driving bit information and the gate driving bit information every 1 data transmission unit.