An electronic system for identifying an article can include a printed memory having a plurality of contact pads electrically coupled to a plurality of landing pads positioned on a first side of a printed circuit board (PCB) substrate. The plurality of landing pads can be electrically coupled to a plurality of endless, concentric contact lines positioned on a second side of the PCB substrate through a plurality of vias that extend through a thickness of the PCB substrate and a plurality of traces that electrically couple the plurality of vias with the plurality of landing pads. To perform a memory operation on the printed memory, contact probes of a reader are physically and electrically contacted with the plurality of concentric contact lines. In some implementations, the memory operation can be performed on the printed memory irrespective of a rotational orientation of the printed memory relative to the reader.

The present disclosure relates to an integrated chip. The integrated chip includes a lower electrode disposed within a dielectric structure over a substrate. A ferroelectric data storage structure is disposed over the lower electrode and an upper electrode is disposed over the ferroelectric data storage structure. One or more stressed sidewall spacers are arranged on opposing sides of the upper electrode. The ferroelectric data storage structure has an orthorhombic phase concentration that varies from directly below the one or more stressed sidewall spacers to laterally outside of the one or more stressed sidewall spacers.

The present disclosure relates to an integrated chip. The integrated chip includes a lower electrode disposed within a dielectric structure over a substrate. A ferroelectric data storage structure is disposed over the lower electrode and an upper electrode is disposed over the ferroelectric data storage structure. One or more stressed sidewall spacers are arranged on opposing sides of the upper electrode. The ferroelectric data storage structure has an orthorhombic phase concentration that varies from directly below the one or more stressed sidewall spacers to laterally outside of the one or more stressed sidewall spacers.

A circular printed memory device and a method for fabricating the circular printed memory device are disclosed. For example, the circular printed memory device includes a base substrate, a plurality of bottom electrodes arranged in a circular pattern on the base substrate, a ferroelectric layer on top of the plurality of bottom electrodes and a single top electrode on the ferroelectric layer that contacts each one of the plurality of bottom electrodes via the ferroelectric layer.

A circular printed memory device and a method for fabricating the circular printed memory device are disclosed. For example, the circular printed memory device includes a base substrate, a plurality of bottom electrodes arranged in a circular pattern on the base substrate, a ferroelectric layer on top of the plurality of bottom electrodes and a single top electrode on the ferroelectric layer that contacts each one of the plurality of bottom electrodes via the ferroelectric layer.

A ferroelectric memory cell (1) and a memory device (100) comprising one or more such cells (1). The ferroelectric memory cell comprises a stack (4) of layers arranged on a flexible substrate (3). Said stack comprises an electrically active part (4a) and a protective layer (11) for protecting the electrically active part against scratches and abrasion. Said electrically active part comprises a bottom electrode layer (5) and a top electrode layer (9) and at least one ferroelectric memory material layer (7) between said electrodes. The stack further comprises a buffer layer (13) arranged between the top electrode layer (9) and the protective layer (11). The buffer layer (13) is adapted for at least partially absorbing a lateral dimensional change (L) occurring in the protective layer (11) and thus preventing said dimensional change (L) from being transferred to the electrically active part (4a), thereby reducing the risk of short circuit to occur between the electrodes.

A ferroelectric memory cell (1) and a memory device (100) comprising one or more such cells (1). The ferroelectric memory cell comprises a stack (4) of layers arranged on a flexible substrate (3). Said stack comprises an electrically active part (4a) and a protective layer (11) for protecting the electrically active part against scratches and abrasion. Said electrically active part comprises a bottom electrode layer (5) and a top electrode layer (9) and at least one ferroelectric memory material layer (7) between said electrodes. The stack further comprises a buffer layer (13) arranged between the top electrode layer (9) and the protective layer (11). The buffer layer (13) is adapted for at least partially absorbing a lateral dimensional change (L) occurring in the protective layer (11) and thus preventing said dimensional change (L) from being transferred to the electrically active part (4a), thereby reducing the risk of short circuit to occur between the electrodes.

A circular printed memory device and a method for fabricating the circular printed memory device are disclosed. For example, the circular printed memory device includes a base substrate, a plurality of bottom electrodes arranged in a circular pattern on the base substrate, a ferroelectric layer on top of the plurality of bottom electrodes and a single top electrode on the ferroelectric layer that contacts each one of the plurality of bottom electrodes via the ferroelectric layer.

A circular printed memory device and a method for fabricating the circular printed memory device are disclosed. For example, the circular printed memory device includes a base substrate, a plurality of bottom electrodes arranged in a circular pattern on the base substrate, a ferroelectric layer on top of the plurality of bottom electrodes and a single top electrode on the ferroelectric layer that contacts each one of the plurality of bottom electrodes via the ferroelectric layer.

A ferroelectric recording medium includes an electrode layer, a ferroelectric recording layer, and a protection layer formed in this order on a substrate, wherein the ferroelectric recording layer includes a ferroelectric layer, the ferroelectric layer has an amorphous structure with short-range order, a distance of the short-range order is equal to or less than 2 nm, and a lattice constant of the amorphous structure and the lattice constant of the material constituting the substrate are lattice-matched within a range of ?10%.