The present disclosure relates to an integrated chip. The integrated chip includes a lower electrode disposed within a dielectric structure over a substrate. A ferroelectric data storage structure is disposed over the lower electrode and an upper electrode is disposed over the ferroelectric data storage structure. One or more stressed sidewall spacers are arranged on opposing sides of the upper electrode. The ferroelectric data storage structure has an orthorhombic phase concentration that varies from directly below the one or more stressed sidewall spacers to laterally outside of the one or more stressed sidewall spacers.

The present disclosure relates to an integrated chip. The integrated chip includes a lower electrode disposed within a dielectric structure over a substrate. A ferroelectric data storage structure is disposed over the lower electrode and an upper electrode is disposed over the ferroelectric data storage structure. One or more stressed sidewall spacers are arranged on opposing sides of the upper electrode. The ferroelectric data storage structure has an orthorhombic phase concentration that varies from directly below the one or more stressed sidewall spacers to laterally outside of the one or more stressed sidewall spacers.

A manufacturing method of a conductive probe that is configured to write information to and read information from a ferroelectric recording medium is provided. The manufacturing method includes: forming, on a conductive material, an insulating layer by oxidizing the conductive material; forming an isolation layer on the insulating layer; applying a photoresist on the isolation layer; forming a hole in the photoresist; etching in the hole to the conductive material; depositing metal on a surface of the conductive material in the hole, thereby obtaining a needle-shaped electrode; and removing the isolation layer. A portion of the needle-shaped electrode protrudes from the surface of the insulating layer.

A manufacturing method of a conductive probe that is configured to write information to and read information from a ferroelectric recording medium is provided. The manufacturing method includes: forming, on a conductive material, an insulating layer by oxidizing the conductive material; forming an isolation layer on the insulating layer; applying a photoresist on the isolation layer; forming a hole in the photoresist; etching in the hole to the conductive material; depositing metal on a surface of the conductive material in the hole, thereby obtaining a needle-shaped electrode; and removing the isolation layer. A portion of the needle-shaped electrode protrudes from the surface of the insulating layer.

Provided are devices and methods for reading data from rotating ferroelectric data storage media using a reader that includes a channel region disposed between a source and a drain. The data bits, stored as dipoles in the ferroelectric media, induce a current flowing through the channel region of the reader from the source to the drain when a bias voltage is applied to the media. The bias voltage can be tuned for desired reader operation, such as enhancing the signal or operating within a linear response regime.

Provided are devices and methods for reading data from rotating ferroelectric data storage media using a reader that includes a channel region disposed between a source and a drain. The data bits, stored as dipoles in the ferroelectric media, induce a current flowing through the channel region of the reader from the source to the drain when a bias voltage is applied to the media. The bias voltage can be tuned for desired reader operation, such as enhancing the signal or operating within a linear response regime.

The present disclosure relates to an integrated chip. The integrated chip includes a lower electrode and a high-k dielectric material disposed over the lower electrode. An upper electrode is disposed over a central region of the high-k dielectric material and a dielectric spacer is arranged on a peripheral region of the high-k dielectric material. The high-k dielectric material includes non-zero concentrations of a tetragonal phase and a monoclinic phase. The non-zero concentrations of the tetragonal phase and the monoclinic phase are lower than a concentration of orthorhombic phase within the high-k dielectric material.

The present disclosure relates to an integrated chip. The integrated chip includes a lower electrode and a high-k dielectric material disposed over the lower electrode. An upper electrode is disposed over a central region of the high-k dielectric material and a dielectric spacer is arranged on a peripheral region of the high-k dielectric material. The high-k dielectric material includes non-zero concentrations of a tetragonal phase and a monoclinic phase. The non-zero concentrations of the tetragonal phase and the monoclinic phase are lower than a concentration of orthorhombic phase within the high-k dielectric material.