A semiconductor memory device includes a logic circuit disposed on a substrate having a cell region and a peripheral region outside the cell region; a source plate defined over the logic circuit; a slit separating the source plate into a cell source plate in the cell region and a dummy source plate in the peripheral region; and a memory cell array defined on the cell source plate. The dummy source plate is maintained at a constant voltage independent of operations of the memory cell array and the logic circuit.

A memory system and storage device are provided, including: an auxiliary power device having at least one capacitor, wherein the at least one capacitor has a first path for leakage current; a charging circuit including a switch connected to the auxiliary power device; and a state determining circuit connected to the auxiliary power device, wherein the state determining circuit includes a path circuit connected in parallel with the at least one capacitor to form a second path having at least one of a resistance lower than a resistance of the first path or a current source.

A storage device may include a memory device and a memory controller. The memory device may include a memory block including a plurality of pages. When a sudden power off is detected in which power supplied to the memory device is abnormally interrupted during a normal program operation on one page among the plurality of pages, the memory controller may control the memory device to perform a dummy program operation on a selected page among the plurality of pages after the sudden power-off. The memory controller may control the memory device to perform the normal program operation and the dummy program operation by using an Incremental Step Pulse Program (ISPP) method. The memory controller may control the memory device to perform the dummy program operation in a smaller number of program loops as compared with the normal program operation.

A memory system, a memory controller and an operating method are disclosed. By dividing a read count table including read count values respectively for a plurality of memory blocks into one or more read count table segments each including one or more read count values of a resolution, and managing one or more flags respectively corresponding to the read count table segments, and set the flag corresponding to the read count table segment in which at least one read count value is changed among the read count table segments, it is possible to minimize additional operational costs required to recover the read count table upon occurrence of an SPO.

A memory system is provided. The memory system includes a memory device having a plurality of memory cells; and a memory controller configured to control the memory device to: store write data in first memory cells from among the plurality of memory cells, identify a current charge amount of a first cell string including at least one of the first memory cells and a current charge amount of a second cell string adjacent to the first cell string, and store dummy data in at least one memory cell connected to the first cell string or the second cell string based on the current charge amount of the first cell string and the current charge amount of the second cell string.

A storage device may include a monitoring module which monitors a characteristic degradation rate of a plurality of blocks included in a cell array of a nonvolatile memory; a group management module which designates the plurality of blocks as one or more groups, on the basis of a monitoring result of the monitoring module; a refresh period management module which determines refresh periods for each of the one or more groups; and a processor which performs refresh on the one or more groups in accordance with the determined refresh periods.

A radiation detection system may include a mobile device having a flash memory. The device may monitor various characteristics of the flash memory to determine when damage to the flash memory has occurred from radiation exposure. The device may associate damage to the flash memory with a radiation dose, and determine a level of radiation to which the memory, and thus the device, has been exposed. The device also may determine a length of time and locations where the radiation exposure has occurred. If the device determines that the level of radiation exposure exceeds a threshold associated with a safe level of radiation exposure for a human user, the device may generate an alert to the user.

Embodiments of the present disclosure relate to a memory system, a memory controller, and a method of operating the memory system. According to embodiments of the present disclosure, a memory system may perform an integrity check operation on target code when information indicating whether a supply voltage supplied to a memory system is maintained at or below a first level for a first unit time is received from a voltage drop detector configured to sense a level of the supply voltage. Accordingly, the memory system is capable of minimizing the time of operation in the state in which a bit-flip occurs and preventing a problem in which irrecoverable data is recorded in a memory device due to malfunction of firmware.

The embodiments provide a method for reading and writing and a memory device. The method includes: applying a read command to the memory device, the read command pointing to address information; reading data to be read out from a memory cell corresponding to the address information pointed to by the read command; storing the address information pointed to by the read command into a memory bit of a preset memory space if an error occurs in the data to be read out, wherein the preset memory space is provided with a plurality of the memory bits, each of the plurality of memory bits being associated with a spare memory cell; and backing up the address information stored in the preset memory space into a non-volatile memory cell according to a preset rule.

Structures and methods are disclosed for shielding magnetically sensitive components. One structure includes a substrate, a bottom shield deposited on the substrate, a magnetoresistive semiconductor device having a first surface and a second surface opposing the first surface, the first surface of the magnetoresistive semiconductor device deposited on the bottom shield, a top shield deposited on the second surface of the magnetoresistive semiconductor device, the top shield having a window for accessing the magnetoresistive semiconductor device, and a plurality of interconnects that connect the magnetoresistive semiconductor device to a plurality of conductive elements.