Methods and systems for handling a single event upset. The methods include, and/or the systems include functionality for, receiving, from a monitored device, data at a first input of an initial state change device; detecting, based on receiving the data, a state change; asserting, based on detecting the state change, an initial state change device enable signal; transferring the first data from the first input to a first output of the initial state change device (which may be operatively connected to a second input of a state hold device); triggering, based on detecting the state change, a delay counter; making a determination that the delay period counted by the delay counter expired without receipt of an error detection signal; and based on the determination, asserting a state hold device enable signal to allow the data to pass from the second input to a second output of the state hold device.

A memory system includes a storage medium including a target memory region having a plurality of memory units; and a controller configured to store data into one or more target memory units, each of which is estimated to take less time to perform a write operation thereon than any of the other memory units among the plurality of memory units, when performing a memory dump operation due to a sudden power off.

A storage device may include a monitoring module which monitors a characteristic degradation rate of a plurality of blocks included in a cell array of a nonvolatile memory; a group management module which designates the plurality of blocks as one or more groups, on the basis of a monitoring result of the monitoring module; a refresh period management module which determines refresh periods for each of the one or more groups; and a processor which performs refresh on the one or more groups in accordance with the determined refresh periods.

A semiconductor memory device includes a first data input/output (I/O) pad, an X-ray detector and a second data I/O pad. The first data I/O pad receives a test signal. The X-ray detector is connected to the first data I/O pad, includes a bipolar junction transistor (BJT) in which a voltage between an input end and an output end changes according to a cumulative X-ray dosage to the semiconductor memory device, and generates a test result signal indicating the voltage between the input and output ends of the BJT based on the test signal. The second data I/O pad is connected to the X-ray detector and outputs the test result signal.

Some embodiments include an integrated assembly having digit lines supported by a base and extending along a first direction. A shield-connection-line is supported by the base and extends along the first direction. Transistor active regions are over the digit lines. Each of the active regions includes a channel region between an upper source/drain region and a lower source/drain region. The lower source/drain regions are coupled with the digit lines. Capacitors are coupled with the upper source/drain regions. Wordlines extend along a second direction which crosses the first direction. The wordlines include gate regions adjacent the channel regions. Shield lines extend along the second direction. The shield lines are above the digit lines and are coupled with the shield-connection-line.

A method for detecting faults in a memory system includes performing an operation on at least one memory cell of the memory system. The method also includes receiving, during performance of the operation, a first clock cycle count for a first pulse of a charge pump associated with the at least one memory cell. The method also includes receiving, during performance of the operation, a second clock cycle count for a second pulse of the charge pump. The method also includes determining whether a fault will occur based on a difference between the first clock cycle count and the second clock cycle count.

A disclosed apparatus and method reduce the likelihood of multiple bit single event upset (SEU) errors in space-deployed memory devices and memory macros. For each memory, a bit selection layer effectively increases the mux of the memory bit table, thereby reducing the word size while increasing the word capacity, without changing the total memory capacity. As a result, the separation between the physical bit storage locations for each word is increased, thereby reducing the likelihood of multiple bit SEU errors. A buffer can be implemented if the memory lacks individual bit write control. The memory can be implemented in a core integrated circuit (IC) of an multi-chip module (MCM) hybrid integrated circuit (HIC), and the bit selection layer and/or buffer can be implemented in a chiplet or chiplets of the MCM-HIC.

A memory system, a memory controller and an operating method are disclosed. By dividing a read count table including read count values respectively for a plurality of memory blocks into one or more read count table segments each including one or more read count values of a resolution, and managing one or more flags respectively corresponding to the read count table segments, and set the flag corresponding to the read count table segment in which at least one read count value is changed among the read count table segments, it is possible to minimize additional operational costs required to recover the read count table upon occurrence of an SPO.

A digital neutron and photon track dosimeter based on three-dimensional Not-And (3D NAND) flash memory may be provided. A plurality of logical addresses respectively associated with a plurality of cells in a 3D NAND flash memory that have been flipped from a first charge state to a second charge state may be determined. Next, the plurality of logical addresses may be converted to a plurality of physical addresses associated with the plurality of cells in the 3D NAND flash memory that have been flipped from the first charge state to the second charge state by radiation. Then a radiation dose proportional to number and plurality of tracks within the plurality of cells associated with the plurality of physical address may be determined.

An armor piece may include a tested material. The armor piece also may include a plurality of electrical contacts distributed about and electrically connected to the tested material. The armor piece further may include a non-volatile memory (NVM) device. The NVM device may be hardened against exposure to x-ray radiation. The NVM device may be configured to store control voltages associated with respective electrical contacts of the plurality of electrical contacts.