A data storage circuit for storing data from volatile memory in response to a power loss, the data storage circuit including an input for receiving a power loss signal in response to a power loss from at least one power source, an input configured to receive data from a volatile memory, a single block of non-volatile matrix of memory cells and a driver circuit coupled to said single row of non-volatile matrix of memory cells. The driver circuit is configured to write data to and read data from said single block of non-volatile matrix of memory cells. The single block of non-volatile matrix of memory cells can be provided as a single row electrically erasable programmable read only memory (EEPROM).

An integrated circuit including a signal line layout is disclosed. A signal line layout may include a number of signal lines configured for conveying a number of signals. The signal line layout may further include a number of shield lines. Each signal line of the number of signal lines may be positioned adjacent a first shield line and a second shield line of the number of the shield lines. Further, first shield line may extend a length of an adjacent signal line and the second shield line may extend less than a length of the adjacent signal line. An electronic system including circuitry having one or more signal line layouts, and methods of forming signal line layout are also described.

A memory system and storage device are provided, including: an auxiliary power device having at least one capacitor, wherein the at least one capacitor has a first path for leakage current; a charging circuit including a switch connected to the auxiliary power device; and a state determining circuit connected to the auxiliary power device, wherein the state determining circuit includes a path circuit connected in parallel with the at least one capacitor to form a second path having at least one of a resistance lower than a resistance of the first path or a current source.

A memory system and storage device are provided, including: an auxiliary power device having at least one capacitor, wherein the at least one capacitor has a first path for leakage current; a charging circuit including a switch connected to the auxiliary power device; and a state determining circuit connected to the auxiliary power device, wherein the state determining circuit includes a path circuit connected in parallel with the at least one capacitor to form a second path having at least one of a resistance lower than a resistance of the first path or a current source.

Apparatuses, systems, and methods related to determination of a match between data values stored by several arrays are described. A system using the data values may manage performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on whether the data values match. For instance, one apparatus described herein includes a plurality of arrays of memory cells formed on a single memory chip. The apparatus further includes comparator circuitry configured to compare data values stored by two arrays selected from the plurality to determine whether there is a match between the data values stored by the two arrays. The apparatus further includes an output component configured to output data values of one of the two arrays responsive to determination of the match between the data values stored by the two arrays.

A storage device may include a monitoring module which monitors a characteristic degradation rate of a plurality of blocks included in a cell array of a nonvolatile memory; a group management module which designates the plurality of blocks as one or more groups, on the basis of a monitoring result of the monitoring module; a refresh period management module which determines refresh periods for each of the one or more groups; and a processor which performs refresh on the one or more groups in accordance with the determined refresh periods.

An electronic apparatus includes a storage device having a plurality of memory blocks including a first memory block; and a controller configured to control the storage device to perform a read operation for the first memory block in response to a read request of a host. The controller controls the storage device to perform a refresh operation for the first memory block based on whether there is a difference value between a current pass read voltage and a previous pass read voltage which were applied to the first memory block when performing the read operation, and whether there is a difference between a current erase/write count and a previous erase/write count for the first memory block.

The purpose of the invention is to compensate for the radiation tolerance of a semiconductor memory. An apparatus (10) for compensating for radiation tolerance comprises: a voltage value acquisition unit (11) that acquires a data retention voltage value that is a maximum voltage value at which data is inverted when a power supply voltage of a semiconductor memory having a latch circuit is lowered; a correction value determination unit (12) that determines a voltage correction value on the basis of a difference between the data retention voltage value and a reference voltage value; and a voltage adjustment unit (13) that adjusts at least one among the power supply voltage and a substrate bias voltage by using the voltage correction value. The reference voltage value is set to be equal to or lower than the data retention voltage value that satisfies a required radiation tolerance.

A storage device may include a monitoring module which monitors a characteristic degradation rate of a plurality of blocks included in a cell array of a nonvolatile memory; a group management module which designates the plurality of blocks as one or more groups, on the basis of a monitoring result of the monitoring module; a refresh period management module which determines refresh periods for each of the one or more groups; and a processor which performs refresh on the one or more groups in accordance with the determined refresh periods.

An integrated circuit (IC) die comprises a sensor, which includes a pulse generator and a pulse expander. The pulse generator comprises gate circuits coupled to each other in an in-series arrangement. An input of the pulse generator is coupled to receive a voltage and the pulse generator is to generate a first signal based on the voltage. The pulse generator is to generate a first pulse of the first signal based on an event wherein radiation from a laser is incident upon the pulse generator. The pulse expander is coupled to receive the first signal from the pulse generator and to generate a second signal based on the first signal, wherein a second pulse of the second signal is based on the first pulse. A first duration of the first pulse is less than a second duration of the second pulse.