A non-volatile memory device includes a substrate having a cell array region and an extension region. A mold structure includes a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on the substrate such that the mold structure has a step shape that steps downwardly in the extension region in a direction away from the cell array region. A channel structure penetrates through the mold structure in the cell array region, and a cell contact structure penetrates through the mold structure in the extension region. A portion of the cell contact structure is in contact with a portion of an uppermost one of the gate electrodes. The cell contact structure includes a first portion in contact with a side surface of the uppermost one of the gate electrodes and a second portion in contact with a top surface of the uppermost one of the gate electrodes. A width of the first portion is smaller than a width of the second portion.

A non-volatile memory device includes a substrate having a cell array region and an extension region. A mold structure includes a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on the substrate such that the mold structure has a step shape that steps downwardly in the extension region in a direction away from the cell array region. A channel structure penetrates through the mold structure in the cell array region, and a cell contact structure penetrates through the mold structure in the extension region. A portion of the cell contact structure is in contact with a portion of an uppermost one of the gate electrodes. The cell contact structure includes a first portion in contact with a side surface of the uppermost one of the gate electrodes and a second portion in contact with a top surface of the uppermost one of the gate electrodes. A width of the first portion is smaller than a width of the second portion.

Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.

Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.

Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

The present disclosure relates to a memory component for a System-on-Chip (SoC) structure including at least a memory array and at least a logic portion for interacting with the memory array and with the SoC structure wherein the memory component is a structurally independent semiconductor device coupled to and partially overlapping the SoC structure.

The present disclosure relates to a memory component for a System-on-Chip (SoC) structure including at least a memory array and at least a logic portion for interacting with the memory array and with the SoC structure wherein the memory component is a structurally independent semiconductor device coupled to and partially overlapping the SoC structure.

Header circuitry for a memory device includes multiple backside power rails that form distinct voltage sources for a plurality of switching devices in the header circuitry. The header circuitry includes at least one region of a first conductivity type. A first section in the first region includes one backside power rail (BPR) that forms a first voltage source that provides a first voltage. A second section in the same first region includes another BPR that forms a second voltage source that provides a second voltage that is different from the first voltage.

Header circuitry for a memory device includes multiple backside power rails that form distinct voltage sources for a plurality of switching devices in the header circuitry. The header circuitry includes at least one region of a first conductivity type. A first section in the first region includes one backside power rail (BPR) that forms a first voltage source that provides a first voltage. A second section in the same first region includes another BPR that forms a second voltage source that provides a second voltage that is different from the first voltage.