Disclosed are a semiconductor memory device and a method of fabricating the same. The device includes a substrate including an active pattern with doped regions, a gate electrode crossing the active pattern between the doped regions, a bit line crossing the active pattern and being electrically connected to one of the doped regions, a spacer on a side surface of the bit line, a first contact coupled to another of the doped regions and spaced apart from the bit line with the spacer interposed therebetween, a landing pad on the first contact, and a data storing element on the landing pad. The another of the doped regions has a top surface, an upper side surface, and a curved top surface that extends from the top surface to the upper side surface. The first contact is in contact with the curved top surface and the upper side surface.

A magnetic memory according to an embodiment includes: a multilayer structure including a semiconductor layer and a first ferromagnetic layer; a first wiring line electrically connected to the semiconductor layer; a second wiring line electrically connected to the first ferromagnetic layer; and a voltage applying unit electrically connected between the first wiring line and the second wiring line to apply a first voltage between the semiconductor layer and the first ferromagnetic layer during a write operation, a magnetization direction of the first ferromagnetic layer being switchable by applying the first voltage.

Semiconductor devices are disclosed. A semiconductor device may include a hybrid transistor configured in a vertical orientation. The hybrid transistor may include a gate electrode, a drain material, a source material, and a channel material operatively coupled between the drain material and the source material. The source material and the drain material include a first material, and the channel material includes a second, different material.

Semiconductor devices are disclosed. A semiconductor device may include a hybrid transistor configured in a vertical orientation. The hybrid transistor may include a gate electrode, a drain material, a source material, and a channel material operatively coupled between the drain material and the source material. The source material and the drain material include a first material, and the channel material includes a second, different material.

An apparatus for separating components of a hard disk drive includes a separating blade mounted on a blade mount and a sensor to detect a gap or seam between a hard disk drive lid and housing. The separating blade defines a bevel edge that can be aligned with the gap or seam. The alignment of the separating blade to the gap is in response to a signal generated by the sensor. In certain instances, the sensor is a laser. Opposing drive rollers are configured to contact a hard disk drive for movement of the hard disk drive into the separating blade.

A production management device, which manages a production schedule of a component mounting line, executes a remote operation mode for remotely operating a component mounter to perform a test operation according to an input operation of an operator, in addition to an automatic production mode in which an automated replacement operation of an automated replacement robot is managed according to the production schedule to produce a component mounting board. The production management device determines, when in the remote operation mode, whether a feeder configured to supply components necessary for the test operation is set in the component mounter, and when the feeder that supplies the necessary components is not set in the component mounter, moves the automated replacement robot to the component mounter and sets the feeder configured to supply the necessary components in the component mounter to cause the component mounter to perform the test operation.

This disclosure provides systems, methods, and devices that support enhanced processing core scheduling schemes. In a first aspect, a system-on-a-chip (SoC) includes at least one processor and at least one memory. The at least one processor is configured to cause the SoC to: receive, at a first deep sleep entity of a first die from a second deep sleep entity of a second die, an indication for the secondary die to enter a deep sleep mode based on a plurality of votes from a plurality of clients of the second die; trigger, by the first deep sleep entity, deep sleep enable logic based on the indication from the secondary die; and trigger, by the first deep sleep entity, a sleep hardening manager deep sleep coordination between dies of the SoC based on the trigger from the first deep sleep entity. Other aspects and features are also claimed and described.