A data transmission circuit, a data transmission method, and a storage apparatus are provided. The data transmission circuit includes a check circuit, a comparison circuit, and a data conversion circuit. The check circuit is configured to generate check code data according to first data on a first data line, and combine the first data and the check code data into second data. The comparison circuit is configured to receive the second data and third data on the second data line, and compare the second data with the third data to output a comparison result indicating whether number of different bits between the second data and the third data exceeds a preset threshold. The data conversion circuit is configured to invert the second data and transmit the inverted second data to the second data line when the comparison result is indicative of exceeding the preset threshold.

A plurality of memory units residing in a first location of a memory device is identified, wherein the first location of the memory device corresponds to a first layer of a plurality of layers of the memory device. It is determined whether a write disturb capability associated with the first location of the memory device satisfies a threshold criterion. Responsive to determining that the write disturb capability associated with the first location of the memory device satisfies the threshold criterion, a plurality of logical addresses associated with the plurality of memory units is remapped to a second location of the memory device, wherein the second location of the memory device corresponds to a second layer of the plurality of layers of the memory device, and wherein a write disturb capability associated with the second location of the memory device does not satisfy the threshold criterion.

A high bandwidth memory system includes a motherboard; and a semiconductor package coupled to the motherboard. The semiconductor package includes a package substrate mounted on the motherboard and including signal lines providing a plurality of channels; a first semiconductor device mounted on the package substrate and including a first physical layer (PHY) circuit; and a second semiconductor device mounted on the package substrate and including a second PHY circuit. The first semiconductor device and the second semiconductor device exchange a data signal with each other through the plurality of channels, the data signal is a multilevel signal having M levels, where M is a natural number greater than 2, and the first PHY circuit compensates for distortion of the channels and performs digital signal processing to compensate for a mismatch between the channels.

A semiconductor chip may include a memory, a power supply line, a noise generator and a switch. The power supply line may include first and second power supply line portions. The power supply line may be configured to provide a power supply signal through each of the first power supply line portion and the second power supply line portion. The noise generator may be connected to the second power supply line portion. The noise generator may be configured to receive the power supply signal from the second power supply line portion, and output a noisy power supply signal based on the power supply signal. The switch may be coupled to the memory, the first power supply line portion, and the noise generator. The switch may be configured to selectively electrically connect the memory to one of the first power supply line portion and the noise generator.

A memory sub-system configured to improve performance using signal and noise characteristics of memory cells measured during the execution of a command in a memory component. For example, the memory component is enclosed in an integrated circuit and has a calibration circuit. The signal and noise characteristics are measured by the calibration circuit as a byproduct of executing the command in the memory component. A processing device separate from the memory component transmits the command to the memory component, and receives and processes the signal and noise characteristics to identify an attribute about the memory component. Subsequently, an operation related to data stored in the memory component can be performed based on the attribute.

A method for operating a memory system includes: collecting, by a memory controller, information on rows that are determined as row-hammer-attacked in a memory by the memory controller; collecting, by the memory, information on rows that are determined as row-hammer-attacked by the memory; confirming, by the memory, that the row collected by the memory controller is the same as the row collected by the memory; and resetting, by the memory, information on the row collected by the memory which is the same as the row collected by the memory controller in response to the confirmation.

A semiconductor device includes a memory circuit, an error correction code circuit, a register circuit and a write circuit. The memory circuit is configured to output, in response to at least one address signal, first data associated with at least one memory cell in the memory circuit. The error correction code circuit is configured to convert the first data to second data and configured to generate error information when the first data is not identical to the second data. The register circuit is configured to output, based on the error information, reset information corresponding to the at least one address signal. The write circuit is configured to reset the at least one memory cell according to the reset information. A method is also disclosed herein.

In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type may be on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g. an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.

In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type may be on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g. an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.

A synergistic approach to mitigating crosstalk in a Dynamic Random-Access Memory (DRAM) implements the use of a random number generator to increment a counter in a probabilistic manner. The counter is formed by reclaiming bytes of a double data rate (DDR) fault isolation feature. The random number generator value may be compared against a predetermined parameter value and a determination may be made whether or not to extract and increment the counter based on a result of the comparison. A logic controller compares the counter value to a predetermined hotness threshold parameter and a flag is set based on an existence of an address match in local memory. Based on the results of the comparison, access to the DRAM is reduced.