A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of a data interface circuit of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of a data interface circuit of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

The present disclosure provides a shift register, a gate driving circuit and a display panel, and belongs to the field of display technology. The shift register of the present disclosure includes: an input circuit configured to precharge and reset a pull-up node; one pull-down control circuit being electrically connected to one pull-down circuit through a pull-down node; the pull-down control circuit being configured to control a potential at the pull-down node under a first power voltage; each pull-down circuit being configured to pull down the potential at the pull-down node in response to a potential at the pull-up node; an output circuit configured to output a clock signal through a signal output terminal in response to the potential at the pull-up node; one first noise reduction circuit connected to one pull-down node.

A semiconductor device, the device comprising: a first silicon layer comprising first single crystal silicon; an isolation layer disposed over said first silicon layer; a first metal layer disposed over said isolation layer; a second metal layer disposed over said first metal layer; a first level comprising a plurality of transistors, said first level disposed over said second metal layer, wherein said isolation layer comprises an oxide to oxide bond surface, wherein said plurality of transistors comprise a second single crystal silicon region; and a plurality of capacitors, wherein said plurality of capacitors comprise functioning as a decoupling capacitor to mitigate power supply noise.

Methods for precharging bit lines using closed-loop feedback are described. In one embodiment, a sense amplifier may include a bit line precharge circuit for setting a bit line to a read voltage prior to sensing a memory cell connected to the bit line. The bit line precharge circuit may include a first transistor in a source-follower configuration with a first gate and a first source node electrically coupled to the bit line. By applying local feedback from the first source node to the first gate, the bit line settling time may be reduced. In some cases, a first voltage applied to the first gate may be determined based on a first current drawn from the first bit line. Thus, the first voltage applied to the first gate may vary over time depending on the conductivity of a selected memory cell connected to the bit line.

Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed.

Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed.

A semiconductor memory device includes: a plurality of memory blocks; a plurality of bit-line sense amplifiers shared by neighboring memory blocks among the plurality of the memory blocks, and suitable for sensing and amplifying data read from memory cells coupled to activated word lines through bit lines, and outputting the amplified data through a plurality of segment data lines; a word line driver suitable for activating word lines of memory blocks that do not share the bit-line sense amplifiers during a test mode; and a weak cell detection circuit suitable for compressing the amplified data transferred through the plurality of the segment data lines for generating compressed data and detecting a weak cell based on the compressed data during the test mode.

A differential interface circuit includes a differential amplifier circuit, a common-mode feedback circuit and a feedback initialization circuit. The differential amplifier circuit is configured to receive and amplify a differential input signal so as to produce an amplified differential output signal. The common-mode feedback circuit is configured to estimate a common-mode level of the differential output signal, to produce a feedback value in response to the estimated common-mode level, and to adjust the differential amplifier circuit using the feedback value. The feedback initialization circuit is configured, in response to detecting that the differential input signal is in a range predefined as abnormal, to temporarily override the common-mode feedback circuit, and instead set the feedback value applied to the differential amplifier circuit to a predefined initialization value.

A memory circuit includes: a memory array unit including a plurality of memory cells and a word line for connecting the plurality of memory cells to each other and applying a drive voltage for driving the memory cells; a drive voltage control unit that generates a drive voltage in which a pre-pulse is set at a timing corresponding to the rising or falling of a voltage signal that changes by a predetermined voltage value in a stepwise manner, applies the drive voltage to a terminal of the word line, and performs control to variably set the time width or the peak value of the pre-pulse in the drive voltage based on address information designating the memory cell at an access destination received from the outside; and a sense amplifier unit that accesses the memory cell designated by the address information.