A memory circuit includes: a memory array unit including a plurality of memory cells and a word line for connecting the plurality of memory cells to each other and applying a drive voltage for driving the memory cells; a drive voltage control unit that generates a drive voltage in which a pre-pulse is set at a timing corresponding to the rising or falling of a voltage signal that changes by a predetermined voltage value in a stepwise manner, applies the drive voltage to a terminal of the word line, and performs control to variably set the time width or the peak value of the pre-pulse in the drive voltage based on address information designating the memory cell at an access destination received from the outside; and a sense amplifier unit that accesses the memory cell designated by the address information.

The present disclosure provides methods, apparatuses, and systems having reduced power noise in a refresh operation. In some embodiments, an operating method includes: performing, in response to receiving a first refresh command, a first normal refresh, at a first refresh timing, in which first N word lines of a plurality of word lines are simultaneously refreshed, and a first target refresh, at a second refresh timing, on at least one first victim word line that is adjacent to a maximum activated word line that is most frequently activated from among the plurality of word lines; and performing, in response to receiving a second refresh command, a second normal refresh, at a third refresh timing, in which second N word lines are simultaneously refreshed, and a second target refresh, at a fourth refresh timing, on at least one second victim word line that is adjacent to the maximum activated word line.

A shift register unit and a drive method thereof, a gate drive circuit, and a display device are provided. A shift register unit includes a first noise reduction circuit, a first input circuit, and an output circuit; the first input circuit is coupled to a first node, and is configured to input a first control signal to the first node in response to a first input signal; the output circuit is coupled to the first node and an output terminal, and is configured to output a first output signal to the output terminal under control of a level of the first node; and the first noise reduction circuit is coupled to the output terminal, and is configured to perform noise reduction on the output terminal in response to a level of the output terminal.

A semiconductor device includes a first wiring having a first portion, a second portion, a third portion provided between the first portion and the second portion, memory cells connected to the third portion of the first wiring, a field effect transistor having a drain connected to the second portion, and a gate, and a second wiring provided in parallel with the first wiring. The third portion of the first wiring includes a fourth portion located nearest to the first portion and a fifth portion located nearest to the second portion. The first wiring further includes a sixth portion disposed between the first portion and the fourth portion. The memory cells include a first memory cell connected to the fourth portion and a second memory cell connected to the fifth portion. The second wiring is electrically connected between the sixth portion and the gate of the field effect transistor.

A receiver that receives a multi-level signal includes a compensation circuit, a sampling circuit, an output circuit and a mode selector. The compensation circuit generates a plurality of data signals and a plurality of reference voltages by compensating intersymbol interference on an input data signal. The sampling circuit generates a plurality of sample signals based on the plurality of data signals and the plurality of reference voltages. The output circuit generates output data based on the plurality of sample signals, and selects a current value of the output data based on a previous value of the output data. The mode selector generates a mode selection signal used to select one of first and second operation modes based on an operating environment. The compensation circuit and the sampling circuit are entirely enabled in the first operation mode, and the compensation circuit and the sampling circuit are partially enabled in the second operation mode.

Apparatuses, systems, and methods for row hammer based cache lockdown. A controller of a memory may include an aggressor detector circuit which determines if addresses are aggressor addresses or not. The controller may include a tracker circuit which may count a number of times an address is identified as an aggressor, and may determine if the aggressor address is a frequent aggressor address based on the count. If the address is a frequent aggressor address, a cache entry associated with the frequent aggressor address may be locked (e.g., for a set amount of time). In some embodiments, the controller may include a second tracker which may determine if the frequent aggressor address is a highly attacked address. An address mapping associated with the highly attacked address may be changed.

A circuit includes a first memory cell and a data control circuit configured to provide first data and second data. The first memory cell has a first port and a second port. The first data is written from the first port to the first memory cell. The second data is based on information of the first data. The second port is configured to write the second data to the first memory cell based on a detection of a write disturb caused by the second port to the first port.

A circuit includes a first memory cell and a data control circuit configured to provide first data and second data. The first memory cell has a first port and a second port. The first data is written from the first port to the first memory cell. The second data is based on information of the first data. The second port is configured to write the second data to the first memory cell based on a detection of a write disturb caused by the second port to the first port.

A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a scrubbing control circuit and a control logic circuit. The memory cell array includes memory cell rows, and each of the memory cell rows including volatile memory cells. The scrubbing control circuit generates scrubbing addresses for performing a normal scrubbing operation on the memory cell rows with a first period based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC engine the scrubbing control circuit to distribute a scrubbing operation on weak codewords dynamically within the refresh operation such that a dynamic allocated scrubbing (DAS) operation is performed with a second period smaller than the first period. An error bit is detected in each of the weak codewords during the normal scrubbing operation or normal read operation on at least one of the memory cell rows.

Disclosed is a memory device, which includes a memory cell, a bit line connected to the memory cell, a controller that generates at least one current control code, a first current generator that generates a first current having a proportional to absolute temperature (PTAT) characteristic, based on the at least one current control code from the controller, a second current generator that generates a second current having a complementary to absolute temperature (CTAT) characteristic, based on the at least one current control code from the controller, a subtractor that generates a third current by subtracting the second current from the first current, and a sense amplifier that controls a load current to be supplied to the bit line based on the third current, and generates a bit line compensation current for compensating for a leakage current of the bit line.