A memory includes S storage blocks, N global bitlines, and a signal amplification circuit. Each of the S storage blocks is connected to the N global bitlines, the N global bitlines are connected to the signal amplification circuit, the signal amplification circuit is configured to amplify electrical signals on the N global bitlines, and each storage block includes N columns of storage units, N local bitlines, and N bitline switches. In each storage block, storage units in an i.sup.th column are connected to an i.sup.th local bitline, the i.sup.th local bitline is connected to an i.sup.th global bitline by using an i.sup.th bitline switch in the N bitline switches. A memory array is fine-grained, so that i.sup.th local bitlines in the S storage blocks can share one global bitline.

A memory device includes a page made up of plural memory cells arranged in a column on a substrate, and a page write operation is performed to hold positive hole groups generated by an impact ionization phenomenon, in a channel semiconductor layer by controlling voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each memory cell contained in the page and a page erase operation is performed to remove the positive hole groups out of the channel semiconductor layer by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region. The first impurity layer of the memory cell is connected with a source line, the second impurity layer is connected with a bit line, one of the first gate conductor layer and the second gate conductor layer is connected with a word line, and another is connected with a drive control line, and the bit line is connected to a sense amplifier circuit via a switch circuit. During a page read operation, page data of a memory cell group selected by the word line is read into a sense amplifier circuit concurrently with a memory cell refresh operation for forming positive hole groups.

A memory device according to the present invention may comprise: a memory cell array in which memory cells are connected in matrix form to word lines and bit lines; a plurality of mergers connected in series to transfer data that is read from a selected memory cell among the memory cells included in the memory cell array and is transformed into one of a direct current form or a pulse form; and a sorter that synchronizes an edge of first output data, output by one of the plurality of mergers, with an edge of a control pulse, thereby delaying the edge of the first output data. First data, which is either data bit “0” or data bit “1”, can be input to the mergers in the form of a direct current of first logic, and second data, which is another piece of data, can be input to the mergers in the form of a pulse that changes from the first logic to the second logic and back to the first logic. When the first data is input, the sorter can allow the first data to pass as-is and output the first data as second output data in the form of a direct current of the first logic. When a first edge that changes from the second logic to the first logic is input, the sorter can delay the first edge by synchronizing the same with a rising edge or falling edge of the control pulse, and output the first edge as the second output data.

Electrically conductive line side-by-side running distance equalization and related apparatuses and systems. An apparatus includes a first sense amplifier, a second sense amplifier, a first pair of lines, and a second pair of lines. The first sense amplifier includes a first pull-up sense amplifier and a first pull-down sense amplifier. The first pair of lines electrically connects a first pull-up sense amplifier of the first sense amplifier to a first pull-down sense amplifier of the first sense amplifier. The second pair of lines electrically connects the second pull-up sense amplifier to the second pull-down sense amplifier. Parallel running distances between lines of the first pair of lines and the second pair of lines are equalized by a wiring twist of the first pair of lines and three wiring twists of the second pair of lines.

A shift register, a driving method, a driving control circuit and a display device. The method comprises: at a data refresh stage (T10), applying to an input signal end (IP) an input signal having a pulse level, applying a control clock pulse signal to a control clock signal end, and applying a noise reduction clock pulse signal to a noise reduction clock signal end; at a noise reduction holding phase (T21-1), applying a fixed voltage signal to the input signal end (IP), applying a fixed voltage signal to the control clock signal end, and applying a fixed voltage signal to the noise reduction clock signal end; and at a noise reduction enhancement stage (T22-1), applying a fixed voltage signal to the input signal end (IP), applying a fixed voltage signal to the control clock signal end, and applying a clock pulse signal to the noise reduction clock signal end.

Embodiments of the present application provide a readout circuit layout structure, a readout circuit, and a memory layout structure. The readout circuit layout structure includes: a readout amplification module, a first processing module, and a second processing module arranged along a preset direction, wherein the readout amplification module is configured to read a voltage of a bit line, and the first processing module and the second processing module are at least configured to perform a noise cancellation on an output signal of the readout amplification module. The readout amplification module includes: a first NMOS region and a first PMOS region arranged close to the first processing module, and a second NMOS region and a second PMOS region arranged close to the second processing module, the first NMOS region, the first PMOS region, the second PMOS region, and the second NMOS region being arranged along the preset direction.

A circuit for signal transmission, memory, and method for signal transmission are provided. The circuit includes: a signal processing circuit, configured to receive an input first signal, obtain a second signal by processing the first signal in a preset processing manner, and take the second signal as an output signal of the signal processing circuit; and a selection circuit, configured to receive the input first signal, the second signal and a control signal, and take the first signal or the second signal as an output signal of the selection circuit according to the control signal.

A memory controller includes an interface and a processor. The interface communicates with memory cells that store data in predefined Programming Voltages (PVs). The processor is configured to produce observation samples that each includes (i) a target sample read from a target memory cell in a target Word Line (WL), and (ii) neighbor samples read from neighbor memory cells. Based on the observation samples, the processor is further configured to jointly estimate Cross-Coupling Coefficients (CCFs), by searching for CCFs that aim to minimize a predefined function of distances calculated between transformed observation samples that have been transformed using the CCFs and combinations of PVs that are closest to the respective transformed observation samples, to apply, based on the CCFs, cross-coupling cancelation to readout samples retrieved from the memory cells to produce enhanced readout samples, and to perform a storage operation related to reading data, using the enhanced readout samples.

A chip includes a processor, a memory, and a storage controller of the memory. There is an access path between the processor and the storage controller, and the processor reads data from or writes data into the memory by using the storage controller through the access path. The chip further includes a shielding circuit. The shielding circuit is configured to shield a signal on the access path when the processor is powered off.

An equalizer circuit, a method for sampling data and a memory are provided. The equalizer circuit includes a first input buffer circuit, a second input buffer circuit and a selecting and sampling circuit. The first input buffer circuit and the second input buffer circuit are respectively connected with the selecting and sampling circuit, and reference voltages used in the first input buffer circuit and the second input buffer circuit are different from each other. The selecting and sampling circuit selects to perform data sampling on a data signal outputted by the first input buffer circuit or the second input buffer circuit according to data outputted previously by the equalizer circuit, and takes sampled data as data outputted currently by the equalizer circuit.