A method for implementing a neural network system in an integrated circuit includes presenting digital pulses to word line inputs of a matrix vector multiplier including a plurality of word lines, the word lines forming intersections with a plurality of summing bit lines, a programmable Vt transistor at each intersection having a gate connected to the intersecting word line, a source connected to a fixed potential and a drain connected to the intersecting summing bit line, each digital pulse having a pulse width proportional to an analog quantity. During a charge collection time frame charge collected on each of the summing bit lines from current flowing in the programmable Vt transistor is summed. During a pulse generating time frame digital pulses are generated having pulse widths proportional to the amount of charge that was collected on each summing bit line during the charge collection time frame.

A memory device includes a memory cell array including a plurality of memory cells on which a programming loop is executed a plurality of times; a voltage generator configured to apply a verifying voltage to the memory cells, for verifying at least one programming state of the memory cells; and a voltage controller configured to control the voltage generator to change a level of the verifying voltage as a program loop count increases, based on temperature information about a temperature inside or outside the memory device.

A memory device includes a memory cell array including a plurality of memory cells on which a programming loop is executed a plurality of times; a voltage generator configured to apply a verifying voltage to the memory cells, for verifying at least one programming state of the memory cells; and a voltage controller configured to control the voltage generator to change a level of the verifying voltage as a program loop count increases, based on temperature information about a temperature inside or outside the memory device.

A processing device of a memory sub-system is configured to determine a current refresh frequency associated with the memory device, the current refresh frequency specifying a rate of performing refresh operations on data stored at the memory device; compute an updated refresh frequency by updating the current refresh frequency based on a criterion reflecting a result of comparing one or more operating parameters of the memory device to their respective threshold values; and perform a refresh operation on data stored at the memory device according to the updated refresh frequency.

A dual-rail memory includes, in part, a memory array that operates using a first supply voltage, and a periphery circuit that operates using a second supply voltage. The periphery circuit includes, in part, a clock generation circuit and a comparator. The dual-rail memory also includes a level shifter that varies the voltage level of a number of signals of the memory between the first and second supply voltages. The clock generation circuit is adapted, among other operations, to generate a read clock signal in response to a read request signal. The level shifter is adapted to supply a reference wordline read signal in response to the read clock signal. The comparator is adapted to select a delay between the read clock signal and the reference wordline read signal in response to a difference between the first and second supply voltages.

Provided is a semiconductor package. The semiconductor package comprises a semiconductor chip on a substrate, a voltage measurement circuit configured to measure an external voltage to be input into the semiconductor chip and a thermoelectric module configured to convert heat released from the semiconductor chip into an auxiliary power, and configured to apply the auxiliary power to the semiconductor chip, the thermoelectric module being separated from the voltage measurement circuit, wherein the voltage measurement circuit is configured to control the thermoelectric module to apply the auxiliary power to the semiconductor chip in response to a change in the external voltage.

Provided is a semiconductor package. The semiconductor package comprises a semiconductor chip on a substrate, a voltage measurement circuit configured to measure an external voltage to be input into the semiconductor chip and a thermoelectric module configured to convert heat released from the semiconductor chip into an auxiliary power, and configured to apply the auxiliary power to the semiconductor chip, the thermoelectric module being separated from the voltage measurement circuit, wherein the voltage measurement circuit is configured to control the thermoelectric module to apply the auxiliary power to the semiconductor chip in response to a change in the external voltage.

Provided is a memory device including a delay circuit having gate insulation films with thicknesses different from each other. The memory device includes a delay circuit configured to input an input signal and output an output signal, and circuit blocks configured to control an operation of reading or writing memory cell data in response to the input signal or the output signal. One of transistors constituting a circuit block has a gate insulation film having such a thickness that an effect of negative biased temperature instability (NBTI) or positive biased temperature instability (PBTI) on the transistors is minimized. The delay circuit may be affected little by a shift in a threshold voltage that may be caused by NTBI or PBTI, and thus, achieve target delay time.

A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.

A method can include, in response to a power supply voltage transition, setting a temperature window to a first temperature range by operation of a temperature circuit formed on a semiconductor device. In response to a temperature of the semiconductor device being determined to be outside of the first temperature range, changing the temperature range of the temperature window until the temperature of the semiconductor device is determined to be within the temperature window.