Stacked semiconductor die assemblies having memory dies stacked between partitioned logic dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a first logic die, a second logic die, and a thermally conductive casing defining an enclosure. The stack of memory dies can be disposed within the enclosure and between the first and second logic dies.

Stacked semiconductor die assemblies having memory dies stacked between partitioned logic dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a first logic die, a second logic die, and a thermally conductive casing defining an enclosure. The stack of memory dies can be disposed within the enclosure and between the first and second logic dies.

A storage device read-disturb-based read temperature map utilization system includes a storage device chassis housing a storage subsystem. A local read temperature utilization subsystem in the storage device chassis determines read disturb information for a plurality of blocks in the storage subsystem, uses it to identify a subset of rows in block(s) in the storage subsystem that have a relatively higher read temperature and, based on those read temperature identifications, generates a local logical storage element read temperature map that identifies a subset of logical storage elements associated with the storage subsystem that have a relatively higher read temperature. The local read temperature utilization subsystem then moves data from first block(s) in the storage subsystem to second block(s) in the storage subsystem based on relative read temperatures identified in the local logical storage element read temperature map.

A processing-in-memory (PIM) device includes a plurality of multiplication and accumulation (MAC) units, each of the MAC units including a memory bank and a MAC operator, and a control circuit configured to control the plurality of MAC units to perform an all MAC mode operation in which MAC operations are performed in all MAC units, among the plurality of MAC units, or a dispersion MAC mode operation in which the MAC operations are performed in some MAC units, among the plurality of MAC units.

A processing-in-memory (PIM) device includes a plurality of multiplication and accumulation (MAC) units, each of the MAC units including a memory bank and a MAC operator, and a control circuit configured to control the plurality of MAC units to perform an all MAC mode operation in which MAC operations are performed in all MAC units, among the plurality of MAC units, or a dispersion MAC mode operation in which the MAC operations are performed in some MAC units, among the plurality of MAC units.

A memory system includes a non-volatile memory having a plurality of memory cells and a controller. The controller is configured to switch a mode for controlling an access operation to the non-volatile memory from a first mode to a second mode, in response to receiving from a host, a first command for instructing the controller to switch the mode from the first mode to the second mode. The access operation controlled according to the second mode improves data retention relative to the access operation controlled according to the first mode.

A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages before a ready/busy signal changing from a ready state to a busy state.

Embodiments of the disclosure, there is provided a method, a system for adjusting the memory, and a semiconductor device. The method for adjusting the memory includes: acquiring a mapping relationship between a temperature of a transistor, an equivalent width-length ratio of a sense amplifier transistor in a sense amplifier and an actual time at which the data is written into the memory; acquiring a current temperature of the transistor; and adjusting the equivalent width-length ratio, based on the current temperature and the mapping relationship, so that the actual time at which the data is written into the memory corresponding to the adjusted equivalent width-length ratio is within a preset writing time.

Embodiments of the disclosure, there is provided a method, a system for adjusting the memory, and a semiconductor device. The method for adjusting the memory includes: acquiring a mapping relationship between a temperature of a transistor, an equivalent width-length ratio of a sense amplifier transistor in a sense amplifier and an actual time at which the data is written into the memory; acquiring a current temperature of the transistor; and adjusting the equivalent width-length ratio, based on the current temperature and the mapping relationship, so that the actual time at which the data is written into the memory corresponding to the adjusted equivalent width-length ratio is within a preset writing time.

A voltage detection circuit and a charge pump circuit using the voltage detection circuit are provided. The voltage detection circuit includes: a voltage raising circuit configured to adjust a voltage to be measured and then output an adjusted voltage, where the adjusted voltage is equal to the sum of the voltage to be measured and a reference voltage; and the reference voltage is generated by a combination of a first voltage with a positive temperature coefficient and a second voltage with a negative temperature coefficient.