A regeneration circuit includes a first inverting circuit and a second inverting circuit. The regeneration circuit also includes a first transistor coupled to an input of the second inverting circuit, and a second transistor coupled to an input of the first inverting circuit, a third transistor and a fourth transistor. A gate of the first transistor and a gate of the fourth transistor are coupled to a first input, and a gate of the second transistor and a gate of the fourth transistor are coupled to a second input. The regeneration circuit further includes a first switch and a second switch. The first switch and the third transistor are coupled in series between a first rail and the first transistor, and the second switch and the fourth transistor are coupled in series between the first rail and the second transistor.

A regeneration circuit includes a first inverting circuit and a second inverting circuit. The regeneration circuit also includes a first transistor coupled to an input of the second inverting circuit, and a second transistor coupled to an input of the first inverting circuit, a third transistor and a fourth transistor. A gate of the first transistor and a gate of the fourth transistor are coupled to a first input, and a gate of the second transistor and a gate of the fourth transistor are coupled to a second input. The regeneration circuit further includes a first switch and a second switch. The first switch and the third transistor are coupled in series between a first rail and the first transistor, and the second switch and the fourth transistor are coupled in series between the first rail and the second transistor.

Broadly speaking, embodiments of the present techniques provide an amplification circuit comprising a sense amplifier and at least one Correlated Electron Switch (CES) configured to provide a signal to the sense amplifier. The sense amplifier outputs an amplified version of the input signal depending on the signal provided by the CES element. The signal provided by the CES element depends on the state of the CES material. The CES element provides a stable impedance to the sense amplifier, which may improve the reliability of reading data from the bit line, and reduce the number of errors introduced during the reading.

Examples include apparatuses and methods related to scan chain operation in sensing circuitry. A number of embodiments include an apparatus comprising an array of memory cells coupled to sensing circuitry having a sense amplifier and a compute component, the sensing circuitry to receive a scan vector and perform a scan chain operation on the scan vector.

Examples include apparatuses and methods related to scan chain operation in sensing circuitry. A number of embodiments include an apparatus comprising an array of memory cells coupled to sensing circuitry having a sense amplifier and a compute component, the sensing circuitry to receive a scan vector and perform a scan chain operation on the scan vector.

A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. In a layout of the sense amplifier, the first and second PMOS transistors are disposed in a central region of the sense amplifier, the first and second NMOS transistors are disposed at opposite sides of the sense amplifier from each other, the first isolation unit and the first offset cancellation unit are disposed between the first PMOS transistor and the first NMOS transistor, and the second isolation unit and the second offset cancellation unit are disposed between the second PMOS transistor and the second NMOS transistor. In other layouts, the locations of the PMOS transistors and NMOS transistors may be reversed.

Systems, apparatuses, and methods related to bit string operations in memory are described. The bit string operations may be performed within a memory array without transferring the bit strings or intermediate results of the operations to circuitry external to the memory array. For instance, sensing circuitry that can include a sense amplifier and a compute component can be coupled to a memory array. A controller can be coupled to the sensing circuitry and can be configured to cause one or more bit strings that are formatted according to a universal number format or a posit format to be transferred from the memory array to the sensing circuitry. The sensing circuitry can perform an arithmetic operation, a logical operation, or both using the one or more bit strings.

The present disclosure relates to an apparatus comprising a non-volatile memory architecture configured to be coupled to a System-on-Chip (SoC) device. The non-volatile memory device coupled to the SoC having a structurally independent structure linked to the SoC includes a plurality of sub arrays forming a matrix of memory cells with associated decoding and sensing circuitry, sense amplifiers coupled to a corresponding sub array, a data buffer comprising a plurality of JTAG cells coupled to outputs of the sense amplifiers; and a scan-chain connecting together the JTAG cells of the data buffer.

The present disclosure relates to an apparatus comprising a non-volatile memory architecture configured to be coupled to a System-on-Chip (SoC) device. The non-volatile memory device coupled to the SoC having a structurally independent structure linked to the SoC includes a plurality of sub arrays forming a matrix of memory cells with associated decoding and sensing circuitry, sense amplifiers coupled to a corresponding sub array, a data buffer comprising a plurality of JTAG cells coupled to outputs of the sense amplifiers; and a scan-chain connecting together the JTAG cells of the data buffer.

A semiconductor device includes a memory array arranged in a matrix, a plurality of word lines provided corresponding to memory cell rows, a word driver for driving one of the plurality of word lines, a plurality of row select lines connected to the word driver, and a row decoder for outputting a row select signal to the plurality of row select lines based on input row address information. According to the embodiment, the semiconductor device can detect a failure of the address decoder in a simple method.