Methods, systems, and devices for selective access for grouped memory dies are described. A memory device may be configured with a select die access protocol for a group of memory dies that share a same channel. The protocol may be enabled by one or more commands from the host device, which may be communicated to each of the memory dies of the group via the channel. The command(s) may indicate a first set of one or more memory dies of the group for which a set of commands may be enabled and may also indicate a second set of one or more memory dies of the group for which at least a subset of the set of commands is disabled. When the select die access mode is enabled, the disabled memory dies may be restricted from performing the subset of commands received via the channel.

A memory device includes: a memory cell array; a first latch; a second latch; a first circuit; and a second circuit. The memory cell array includes first, second, and third columns associated with first, second, and third addresses, respectively. The first latch stores the first address and is associated with a fourth address. The second latch stores the second address and is associated with a fifth address. The fourth address and the fifth address are in an ascending order. The first circuit selects the third column in place of the first column based on the first address. The second circuit determines whether or not the first address and the second address are in an ascending order.

A system comprising includes a memory device having memory cells a processing device, operatively coupled to the memory device. The processing device is to perform operations including: determining a length of time the memory device has been powered off; and in response to determining that the length of time satisfies a threshold value: for each of multiple groups of memory cells, asserting a corresponding flag; determining, based on the length of time, one or more adjusted demarcation voltages to be used in reading a state of the multiple groups of memory cells; and storing the one or more adjusted demarcation voltages for use in performing memory operations.

A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

The present disclosure includes apparatuses and methods related to bank coordination in a memory device. A number of embodiments include a method comprising concurrently performing a memory operation by a threshold number of memory regions, and executing a command to cause a budget area to perform a power budget operation associated with the memory operation.

Novel connection between neurons of a neural network is provided. A perceptron included in the neural network includes a plurality of neurons; the neuron includes a synapse circuit and an activation function circuit; and the synapse circuit includes a plurality of memory cells. A bit line selected by address information for selecting a memory cell is shared by a plurality of perceptrons. The memory cell is supplied with a weight coefficient of an analog signal, and the synapse circuit is supplied with an input signal. The memory cell multiplies the input signal by the weight coefficient and converts the multiplied result into a first current. The synapse circuit generates a second current by adding a plurality of first currents and converts the second current into a first potential. The activation function circuit is a semiconductor device that converts the first potential into a second potential by a ramp function and supplies the second potential as an input signal of the synapse circuit included in the perceptron in a next stage.

Technologies for performing a quick reliability scan include, for a particular block of a set of blocks of different block types. Each block of the set of blocks includes pages of memory of a physical memory device. A subset of the pages of the block is identified. The block is scanned by scanning the subset of the plurality of pages of the block for a fold condition. A page of the subset of the plurality of pages is determined to have the fold condition. After the set of blocks has been scanned, the folding of the block that includes the page that has been determined to have the fold condition is requested.

A memory device includes a page made up of plural memory cells arranged in a column on a substrate. A page write operation is performed to hold positive hole groups generated by an impact ionization phenomenon, in a channel semiconductor layer by controlling voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer of each memory cell contained in the page and a page erase operation is performed to remove the positive hole groups out of the channel semiconductor layer by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer. The first impurity layer of the memory cell is connected with a source line, the second impurity layer is connected with a bit line, one of the first gate conductor layer and the second gate conductor layer is connected with a word line, and another is connected with a drive control line. The bit line is connected to a sense amplifier circuit via a switch circuit. At least one of word lines is selected and a refresh operation is performed to return the voltage of the channel semiconductor layer of the selected word line to the first data retention voltage by controlling voltages applied to the selected word line, the drive control line, the source line, and the bit line and thereby forming the positive hole groups by an impact ionization phenomenon in the channel semiconductor layer of the memory cell in which the voltage of the channel semiconductor layer is set to the first data retention voltage using the page write operation. The refresh operation is performed, with the switch circuit kept in a nonconducting state, concurrently with a page read operation of reading page data of a first memory cell group belonging to a first page into the sense amplifier circuit.

The present disclosure includes apparatuses and methods for in data path compute operations. An example apparatus includes an array of memory cells. Sensing circuitry is selectably coupled to the array. A plurality of shared input/output (I/O) lines provides a data path. The plurality of shared I/O lines selectably couples a first subrow of a row of the array via the sensing circuitry to a first compute component in the data path to move a first data value from the first subrow to the first compute component and a second subrow of the respective row via the sensing circuitry to a second compute component to move a second data value from the second subrow to the second compute component. An operation is performed on the first data value from the first subrow using the first compute component substantially simultaneously with movement of the second data value from the second subrow to the second compute component.