A method for writing to a non-volatile electronic memory with data words and assigned pieces of index information. The non-volatile electronic memory is initially filled exclusively with empty data frames. The empty data frames are overwritable with multi-data frames and/or individual data frames. A multi-data frame includes a selectable number of sequentially stored data words, and a multi-data frame header. A frame-type marker, the number of data words, and a selectable start index are stored in the multi-data frame header so that each data word is assignable a unique index value from an index interval by incrementing or decrementing. An individual data frame includes one data word and an individual data frame header. A frame-type marker and a selectable index value for the one data word of the individual data frame are stored in the individual data frame header.

A computing system for supporting a plurality of different types of memory devices includes a memory voltage regulator. The memory voltage regulator adjusts a supply voltage to a requisite voltage for a detected memory device based on serial presence detect (SPD) data. The computing system further includes a memory controller that supports a plurality of types of memory devices. The memory controller receives data regarding the type of the detected memory device, and controls input/output signals relative to the type of the detected memory device based on the SPD data and the GPIO data of the detected memory device.

A computing system for supporting a plurality of different types of memory devices includes a memory voltage regulator. The memory voltage regulator adjusts a supply voltage to a requisite voltage for a detected memory device based on serial presence detect (SPD) data. The computing system further includes a memory controller that supports a plurality of types of memory devices. The memory controller receives data regarding the type of the detected memory device, and controls input/output signals relative to the type of the detected memory device based on the SPD data and the GPIO data of the detected memory device.

A programmable logic array (PLA) is disclosed employing programming logic tile (PLT), System On Chip (SOC) interface bus, Input Output (IO) blocks and Logic Processing Blocks (LPB). SOC processors using SOC interface bus program PLT successively using different configuration memory bank values to realize a logic not limited by the PLT resource counts. Configuration memory blocks comprising of multiple configuration memory banks and configuration programming control logic remove logic processing penalty due to configuration delays. PLT comprises of Programmable Logic Cells (PLC), Programmable Logic Interface (PLY), Embedded Array Blocks (EAB) and configuration memory block. PLA comprises of PLT, IO blocks, SOC interface bus and LPB. PLA accelerates user functionality in as SOC. IO blocks are used to stream data from other SOC components. LPB use PLT to accelerate user specific functionality.

A programmable logic array (PLA) is disclosed employing programming logic tile (PLT), System On Chip (SOC) interface bus, Input Output (IO) blocks and Logic Processing Blocks (LPB). SOC processors using SOC interface bus program PLT successively using different configuration memory bank values to realize a logic not limited by the PLT resource counts. Configuration memory blocks comprising of multiple configuration memory banks and configuration programming control logic remove logic processing penalty due to configuration delays. PLT comprises of Programmable Logic Cells (PLC), Programmable Logic Interface (PLY), Embedded Array Blocks (EAB) and configuration memory block. PLA comprises of PLT, IO blocks, SOC interface bus and LPB. PLA accelerates user functionality in as SOC. IO blocks are used to stream data from other SOC components. LPB use PLT to accelerate user specific functionality.

Systems, apparatuses, and methods related to organizing data to correspond to a matrix at a memory device are described. Data can be organized by circuitry coupled to an array of memory cells prior to the processing resources executing instructions on the data. The organization of data may thus occur on a memory device, rather than at an external processor. A controller coupled to the array of memory cells may direct the circuitry to organize the data in a matrix configuration to prepare the data for processing by the processing resources. The circuitry may be or include a column decode circuitry that organizes the data based on a command from the host associated with the processing resource. For example, data read in a prefetch operation may be selected to correspond to rows or columns of a matrix configuration.

A computer-implemented method includes an act of configuring hardware to cause at least a part of the hardware to operate as a double data rate (DDR) memory controller, and to produce a capture clock to time a read data path, where a timing of the capture clock is based on a first clock signal of a first clock, delay the first clock signal to produce a delayed first clock signal, adjust the delay such that at least one clock edge of the delayed first clock signal is placed nearer to at least one clock edge of at least one data strobe (DQS), or at least one signal dependent on a DQS timing, and produce a modified timing of the capture clock based on the delay of the first clock signal.

The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

A memory module is operable in a computer system having a memory controller and a system bus and comprises memory devices organized in one or more ranks and in a plurality of groups, and circuits configurable to receive from the memory controller a system clock and input control and address (C/A) signals, generate a module clock signal and module C/A signals in response to the system clock and input C/A signals, generate a plurality of local clock signals corresponding, respectively, to the plurality of groups of memory devices, and output the plurality of local clock signals to respective groups of the memory devices. A respective local clock signal has a respective phase relationship with the module clock signal and is output to a corresponding group of the memory devices that includes at least one corresponding memory device in each of the one or more ranks.

A system on chip (SoC) includes an internal read-only memory (ROM) configured to store a first boot loader; a first internal static random access memory (SRAM) configured to receive a second boot loader output from a booting device, store the second boot loader, and perform a booting sequence according to control of the first boot loader; a second internal SRAM configured to receive a third boot loader output from the booting device, store the third boot loader, and perform a wake-up sequence according to control of the first boot loader; and a dynamic random access memory (DRAM) controller configured to load an operating system (OS) from the booting device into a DRAM according to control of the second boot loader.