In an anti-fuse memory reading circuit with controllable reading time, a reading time control circuit generates a control signal corresponding to reading time. Based on a clock signal, a programmable reading pulse generation circuit generates a reading pulse with a pulse width corresponding to the control signal. Based on the reading pulse and the control signal, the reading amplification circuit selects a pull-up current source corresponding to the reading time, pulls up a voltage on a bit line (BL) of an anti-fuse memory cell, reads data stored in the anti-fuse memory cell starting from a rising edge of the reading pulse, and latches the read data at a falling edge of the reading pulse. The anti-fuse memory reading circuit can generate a reading pulse with a corresponding pulse width and a pull-up current source with a corresponding size based on the required reading time.

In an anti-fuse memory reading circuit with controllable reading time, a reading time control circuit generates a control signal corresponding to reading time. Based on a clock signal, a programmable reading pulse generation circuit generates a reading pulse with a pulse width corresponding to the control signal. Based on the reading pulse and the control signal, the reading amplification circuit selects a pull-up current source corresponding to the reading time, pulls up a voltage on a bit line (BL) of an anti-fuse memory cell, reads data stored in the anti-fuse memory cell starting from a rising edge of the reading pulse, and latches the read data at a falling edge of the reading pulse. The anti-fuse memory reading circuit can generate a reading pulse with a corresponding pulse width and a pull-up current source with a corresponding size based on the required reading time.

A semiconductor device includes a memory bank. The memory bank includes a plurality N of memory arrays and a local control circuit. Each memory array includes a plurality of bit cells configured to store bits of information and connected between a plurality of bit lines and a plurality of complement bit lines. The local control circuit is configured to pre-charge the bit lines and the complement bit lines at most N-1 memory array at a time. A method of operating the semiconductor device is also disclosed.

A semiconductor device includes a memory bank. The memory bank includes a plurality N of memory arrays and a local control circuit. Each memory array includes a plurality of bit cells configured to store bits of information and connected between a plurality of bit lines and a plurality of complement bit lines. The local control circuit is configured to pre-charge the bit lines and the complement bit lines at most N-1 memory array at a time. A method of operating the semiconductor device is also disclosed.

A memory circuit includes a reference node configured to carry a reference voltage having a reference voltage level, a power supply node configured to carry a power supply voltage having a power supply voltage level, a bit line coupled with a plurality of memory cells, a write circuit configured to charge the bit line by driving a voltage level on the bit line toward the power supply voltage level with a first current, and a switching circuit coupled between the power supply node and the bit line. The switching circuit is configured to receive the voltage level on the bit line, and responsive to a difference between the voltage level received on the bit line and the power supply voltage level being less than or equal to a threshold value, drive the voltage level on the bit line toward the power supply voltage level with a second current.

A memory circuit includes a reference node configured to carry a reference voltage having a reference voltage level, a power supply node configured to carry a power supply voltage having a power supply voltage level, a bit line coupled with a plurality of memory cells, a write circuit configured to charge the bit line by driving a voltage level on the bit line toward the power supply voltage level with a first current, and a switching circuit coupled between the power supply node and the bit line. The switching circuit is configured to receive the voltage level on the bit line, and responsive to a difference between the voltage level received on the bit line and the power supply voltage level being less than or equal to a threshold value, drive the voltage level on the bit line toward the power supply voltage level with a second current.

Numerous embodiments are disclosed for splitting a physical array into multiple arrays for separate vector-by-matrix multiplication (VMM) operations. In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns; and a plurality of sets of output lines, where each column contains a set of output lines; wherein each row is coupled to only one output line in the set of output lines for each column.

Numerous embodiments are disclosed for splitting a physical array into multiple arrays for separate vector-by-matrix multiplication (VMM) operations. In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns; and a plurality of sets of output lines, where each column contains a set of output lines; wherein each row is coupled to only one output line in the set of output lines for each column.

Provided herein may be a page buffer, a memory device having the page buffer, and a method of operating the memory device. The page buffer may include a precharger configured to precharge a bit line to a precharge level, a comparison signal output circuit configured to generate a first output signal by comparing a voltage of the bit line with a reference voltage, a pulse width control circuit configured to generate a second output signal by increasing a pulse width of a pulse of the first output signal by a preset multiple, and a register configured to sense data based on a pulse width of the second output signal and output the sensed data.

Provided herein may be a page buffer, a memory device having the page buffer, and a method of operating the memory device. The page buffer may include a precharger configured to precharge a bit line to a precharge level, a comparison signal output circuit configured to generate a first output signal by comparing a voltage of the bit line with a reference voltage, a pulse width control circuit configured to generate a second output signal by increasing a pulse width of a pulse of the first output signal by a preset multiple, and a register configured to sense data based on a pulse width of the second output signal and output the sensed data.