A method for finding an optimum read voltage includes acquiring difference values between state bit counts of different positions. A direction for finding the optimum read voltage is determined based on the difference values. An offset for finding the optimum read voltage is determined based on correspondence between a difference value of bit count and offset. Reading is performed with the offset applied to a current read reference voltage, wherein upon read-success, the current reference voltage superimposed with the offset is the optimum read voltage, and upon read-error, new first and second positions are obtained based on the direction and the offset for finding the optimum read voltage until reading becomes successful.

A nonvolatile memory device includes an array of magnetic memory cells, and control logic circuit having a voltage generator therein, which is configured to generate a gate voltage. A row decoder is provided, which is connected by word lines to the array of magnetic memory cells, and has a word line driver driven therein, which is responsive to the gate voltage. A column decoder is provided, which is connected by bit lines and source lines to the array of magnetic memory cells. A write driver is provided, which has a write voltage generating circuit therein that is configured to output a write voltage, in response to: (i) a reference voltage generated using a replica magnetic memory cell, and (ii) a feedback voltage generated using a magnetic memory cell in which a write operation is to be performed.

A nonvolatile memory device includes an array of magnetic memory cells, and control logic circuit having a voltage generator therein, which is configured to generate a gate voltage. A row decoder is provided, which is connected by word lines to the array of magnetic memory cells, and has a word line driver driven therein, which is responsive to the gate voltage. A column decoder is provided, which is connected by bit lines and source lines to the array of magnetic memory cells. A write driver is provided, which has a write voltage generating circuit therein that is configured to output a write voltage, in response to: (i) a reference voltage generated using a replica magnetic memory cell, and (ii) a feedback voltage generated using a magnetic memory cell in which a write operation is to be performed.

A memory device includes a plurality of magnetoresistive random-access memory (MRAM) cells including a first one-time programmable (OTP) MRAM cell. A first OTP select transistor is connected to the first OTP MRAM cell. The first OTP select transistor configured to selectively apply a breakdown current to the first OTP MRAM cell to write the first OTP MRAM cell to a breakdown state.

A system is provided. The system includes a multiply-and-accumulate circuit and a local generator. The multiply-and-accumulate circuit is coupled to a memory array and generates a multiply-and-accumulate signal indicating a computational output of the memory array. The local generator is coupled to the memory array and generates at least one reference signal at a node in response to one of a plurality of global signals that are generated according to a number of the computational output. The local generator is further configured to generate an output signal according to the signal and a summation of the at least one reference signal at the node.

A system is provided. The system includes a multiply-and-accumulate circuit and a local generator. The multiply-and-accumulate circuit is coupled to a memory array and generates a multiply-and-accumulate signal indicating a computational output of the memory array. The local generator is coupled to the memory array and generates at least one reference signal at a node in response to one of a plurality of global signals that are generated according to a number of the computational output. The local generator is further configured to generate an output signal according to the signal and a summation of the at least one reference signal at the node.

The present invention includes apparatus and a method for reading one or more data states from an integrated circuitry memory cell, including the steps of connecting the memory cell to a bit line which is connected to an amplifier having an offset control which introduces an offset during the sensing portion of a read cycle to identify a data state stored in the memory cell.

The present invention includes apparatus and a method for reading one or more data states from an integrated circuitry memory cell, including the steps of connecting the memory cell to a bit line which is connected to an amplifier having an offset control which introduces an offset during the sensing portion of a read cycle to identify a data state stored in the memory cell.

A nonvolatile memory apparatus may include a control circuit, a sense amplifier, and a reference generator. The control circuit may apply a read voltage across a target memory cell through a selected global bit line and a selected global word line. The sense amplifier may generate an output signal by comparing voltage levels of the selected global word line and a reference line. The reference generator may change the voltage level of the reference line by charging and discharging a capacitor that is coupled to the reference line.

Methods, systems, and devices for sense amplifier with digit line multiplexing are described. A method includes precharging an input and an output of an amplifier stage of a sense component to a first voltage based on a read operation associated with a memory cell. The method includes precharging a first side and a second side of a latch stage of the sense component to the first voltage based on precharging the output of the amplifier stage to the first voltage, the latch stage coupled with the amplifier stage. The method may also include coupling a second voltage from a digit line associated with the memory cell to the input of the amplifier stage, the amplifier stage generating a third voltage on the output based on coupling the second voltage to the input, and the latch stage latching a logic value associated with the memory cell based on the third voltage.