A signal receiving device includes a sampling device configured to sample an input signal to output a plurality of sampling values, and an output circuit configured to output data based on the sampling values. The output circuit outputs the data by performing majority voting based on first to third sampling values of the sampling values in response to a first control signal, and outputs the data and first and second error count signals based on the first sampling value and fourth and fifth sampling values of the sampling values in response to a second control signal. The first error count signal is generated by comparing the first sampling value sampled under a reference condition with the fourth sampling value sampled under a first offset condition, and the second error count signal is generated by comparing the first sampling value with the fifth sampling value sampled under a second offset condition.

A memory controller includes a first receiver configured to compare a read reference voltage with a piece of data received through a first data line and output a first piece of data; a first duty adjuster configured to adjust a duty of the first piece of data; a second receiver configured to compare the read reference voltage with a piece of data received through a second data line and output a second piece of data; a second duty adjuster configured to adjust a duty of the second piece of data; and a training circuit configured to perform a training operation on pieces of data received through a plurality of data lines, to obtain a target read reference voltage for each piece of data and correct a duty of each piece of data based on a level of the target read reference voltage for each piece of data.

A memory device includes a memory cell array with a plurality of memory cells that are connected to a plurality of word lines and a plurality of strings; and a peripheral circuit for performing a program operation on selected memory cells, among the plurality of memory cells, connected to a selected word line. While the peripheral circuit applies a pass voltage to the selected word line during the program operation to turn on the selected memory cells, the peripheral circuit is configured to apply a select voltage to an unselected source line to turn on a source select transistor and configured to apply a ground voltage to an unselected drain select line.

A comparison circuit includes a comparison module, a state judgment module and a state storage module. The comparison module includes a first input end connected to a voltage to be measured and a second input end connected to a reference voltage. The state judgment module includes a first input end connected to a first output end of the comparison module and a second input end connected to a second output end of the comparison module. The state storage module includes an input end connected to the first output end of the comparison module and an enable end connected to an output end of the state judgment module. The embodiments of the disclosure may improve processing efficiency of the comparison circuit.

A storage circuit (11) includes memory cells (MCij), each of which includes an MTJ element, and reference cells (RCi), each of which includes a series circuit of an MTJ element set to a low-resistance state and a linear resistor (FR). A RW circuit (23j) that includes a sense amplifier is provided in each column of a memory cell array (21), and compares a data voltage on a corresponding bit line (BLj) with a reference voltage. The sense amplifier includes a pair of PMOS transistors to which the data voltage and the reference voltage are applied, a CMOS sense latch that is connected to a current path of the PMOS transistors.

A temperature sensing circuit of a data storage system includes a temperature sensor, a digital-to-analog circuit, and a reference generation and trimming circuit configured to generate a common mode voltage (VCM), a positive reference voltage (VREFP), and a negative reference voltage (VREFN) using a single band gap reference signal. The trimming circuit is configured to trim the VCM, VREFP, and VREFN by adjusting a VC trim signal to increase the VCM until a VCM error is below a threshold; adjusting a high temperature trim signal to increase the VREFP and decrease the VREFN until a digital temperature signal associated with the digital-to-analog circuit attains a predetermined accuracy level for a first temperature; and adjusting a low temperature trim signal to increase the VREFP, VCM, and VREFN until the digital temperature signal attains a predetermined accuracy level for a second temperature.

A nonvolatile memory device includes a memory block with an unused line connected to dummy cells and used lines connected to normal cells, and a controller which applies an erase voltage to the memory block, applies an unused line erase voltage to the unused line, and applies a word line erase voltage to the used lines during an erase operation. The dummy cells are not programmed during a program operation while the normal cells are programmed, the unused line erase voltage transits from a first voltage to a floating voltage at a first time point, and the controller reads the dummy cells and controls at least one of the magnitude of the first voltage and the first time point based on the result of reading the dummy cells.

Methods and apparatuses with counter-based reading are described. A memory cells of a codeword are accessed and respective voltages are generated. A reference voltage is generated and a logic state of each memory cell is determined based on the reference voltage and the respective generated cell voltage. The reference voltage is modified until a count of memory cells determined to be in a predefined logic state with respect to the last modified reference voltage value meets a criterium. In some embodiments the criterium may be an exact match between the memory cells count and an expected number of memory cells in the predefined logic state. In other embodiments, an error correction (ECC) algorithm may be applied while the difference between the count of cells in the predefined logic state and the expected number of cells in that state does not exceed a detection or correction power of the ECC.

Methods and apparatuses with counter-based reading are described. A memory cells of a codeword are accessed and respective voltages are generated. A reference voltage is generated and a logic state of each memory cell is determined based on the reference voltage and the respective generated cell voltage. The reference voltage is modified until a count of memory cells determined to be in a predefined logic state with respect to the last modified reference voltage value meets a criterium. In some embodiments the criterium may be an exact match between the memory cells count and an expected number of memory cells in the predefined logic state. In other embodiments, an error correction (ECC) algorithm may be applied while the difference between the count of cells in the predefined logic state and the expected number of cells in that state does not exceed a detection or correction power of the ECC.

A semiconductor device includes a transmission and reception circuit and a control circuit. The transmission and reception circuit transmits and receives a signal to and from a semiconductor memory device. The control circuit acquires threshold voltage distribution information of a memory element connected to a word line for read disturb detection to which a second voltage higher than a first voltage applied to an adjacent word line adjacent to a read target word line during a read operation is applied and determines an influence of read disturb based on the threshold voltage distribution information.