In some examples, a master die may receive data from one or more slave die. The master die may provide data from the master die and the data from the one or more slave die to a plurality of output terminals. Data from the master die may be provided for a portion of a data burst and data from the slave die may be provided for another portion of the data burst. In some examples, a master die may provide data to one or more slave die. The master die may provide data to the master die and the data to the one or more slave die from a plurality of input terminals. Data from the input terminals may be provided to the slave die for a portion of a data burst and data may be provided from the master die for another portion of the data burst.

Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

Disclosed herein is a sense amplifier. In one aspect, the sense amplifier includes a first pair of cross-coupled transistors and a second pair of cross-coupled transistors coupled to a first port and a second port of the sense amplifier. In one aspect, the sense amplifier includes a first access transistor coupled between a first input line and the first port. In one aspect, the sense amplifier includes a second access transistor coupled between a second input line and the second port. In one aspect, the first pair of cross-coupled transistors includes a first transistor and a second transistor cross-coupled with each other. In one aspect, a source electrode of the first transistor is directly coupled to the first input line, and a source electrode of the second transistor is directly coupled to the second input line.

Disclosed herein is a sense amplifier. In one aspect, the sense amplifier includes a first pair of cross-coupled transistors and a second pair of cross-coupled transistors coupled to a first port and a second port of the sense amplifier. In one aspect, the sense amplifier includes a first access transistor coupled between a first input line and the first port. In one aspect, the sense amplifier includes a second access transistor coupled between a second input line and the second port. In one aspect, the first pair of cross-coupled transistors includes a first transistor and a second transistor cross-coupled with each other. In one aspect, a source electrode of the first transistor is directly coupled to the first input line, and a source electrode of the second transistor is directly coupled to the second input line.

An electronic device includes: a system-on-chip (SoC) including a processor, a near-memory controller controlled by the processor, and a far-memory controller controlled by the processor; a near-memory device including a first memory channel configured to communicate with the near-memory controller and operate in a first mode of a plurality of modes, and a second memory channel configured to communicate with the near-memory controller and operate in a second mode different from the first mode from among the plurality of modes; and a far-memory device configured to communicate with the far-memory controller. The first memory channel is further configured to, based on a command from the near-memory controller, change an operation mode from the first mode to the second mode.

Methods, apparatuses, and systems related to coordinating a set of timing-critical operations across parallel processing pipelines are described. The coordination may include selectively using (1) circuitry associated with a corresponding pipeline to generate enable signals associated with the timing critical operations when a separation between the operations corresponds to a number of pipelines or (2) circuitry associated with a non-corresponding or another pipeline when the separation is not a factor of the number of pipelines.

A method of operating a memory device including receiving a multilevel signal having M levels transmitted by an external controller through a clock receiving pin, where M is a natural number greater than 2, and decoding the multilevel signal to restore at least one of Data Bus Inversion (DBI) data, Data Mask (DM) data, Cyclic Redundancy Check (CRC) data, or Error Correction Code (ECC) data may be provided. The multilevel signal is a clock signal transmitted by the external controller, and is a signal swinging based on an intermediate reference signal that is an intermediate value between a minimum level and a maximum level among the M levels.

An operating method for a dynamic random access memory (DRAM) obtains a plurality of first sub-commands of a first activate command via a command bus, and obtaining a plurality of first address information regarding a plurality of first portions of a first row address of a specific bank via an address bus. Each of the first sub-commands corresponds to an individual first portion of the first row address of the specific bank. The method further combines the first portions of the first row address of the specific bank in response to a specific sub-command of the first sub-commands, so as to obtain a first complete row address; and obtains an access command via the command bus.

Apparatuses, memory modules, and methods for performing intra-module data bus inversion operations are described. An example apparatus include a memory module comprising a data bus inversion (DBI) and buffer circuit and a plurality of memories. The DBI and buffer circuit configured to encode a block of data received by the memory module and to provide DBI data and a corresponding DBI bit to a respective memory of the plurality of memories.

Apparatuses, memory modules, and methods for performing intra-module data bus inversion operations are described. An example apparatus include a memory module comprising a data bus inversion (DBI) and buffer circuit and a plurality of memories. The DBI and buffer circuit configured to encode a block of data received by the memory module and to provide DBI data and a corresponding DBI bit to a respective memory of the plurality of memories.