A method for addressing memory device data arranged in rows and columns indexed by a first number of row address bits and a second number of column address bits, and addressed by a row command specifying a third number of row address bits followed by a column command specifying a fourth number of column address bits, the first number being greater than the third number or the second number being greater than the fourth number, includes: splitting the first number of row address bits into first and second subsets, and specifying the first subset in the row command and the second subset in a next address command when the first number is greater than the third number; otherwise splitting the second number of column address bits into third and fourth subsets, and specifying the fourth subset in the column command and the third subset in a previous address command.

A counter readout circuit includes a plurality of counter registers and an output data computing unit. The plurality of counter registers, each includes a counter which counts per clock signal cycle. The output data computing unit includes a computing unit which adds, for output, the counter value of a counter register to the total clock count from a first timing to a second timing. The counter register is selected from the plurality of counter registers. The first timing is common to all of the plurality of counter registers. The second timing is a timing of selection of the selected counter register.

A semiconductor memory device includes a cell array including a plurality of word lines; a plurality of address storing circuits suitable for sequentially storing a sampling address as one of a plurality of latch addresses, and sequentially outputting each of the latch addresses as a target address according to a refresh command; a duplication decision circuit suitable for preventing the sampling address from being stored in the address storing circuits when the sampling address is identical to any of the latch addresses stored in the address storing circuits; and a row control circuit suitable for refreshing one or more word lines based on the target address in response to the refresh command.

An address counting circuit includes a shared address counting circuit configured to generate a first shared address and a second shared address by counting an external start address at a first edge and a second edge of a counting clock signal and a latch circuit including a plurality of latches configured to share the first shared address and the second shared address, respectively and generate a plurality of column addresses by latching the first shared address and second shared address according to a plurality of latch clock signals.

A semiconductor memory device includes a cell array including a plurality of word lines; a plurality of address storing circuits suitable for sequentially storing a sampling address as one of a plurality of latch addresses, and sequentially outputting each of the latch addresses as a target address according to a refresh command; a duplication decision circuit suitable for preventing the sampling address from being stored in the address storing circuits when the sampling address is identical to any of the latch addresses stored in the address storing circuits; and a row control circuit suitable for refreshing one or more word lines based on the target address in response to the refresh command.

A system includes a memory array with sub-blocks, each sub-block having groups of memory cells. A processing device, operatively coupled with the memory array, is to perform operations including performing, after a wordline is programmed through the sub-blocks, scanning of the wordline. The scanning includes selecting, to sample first data of the wordline, a first group of the groups of memory cells of a first sub-block of the sub-blocks; selecting, to sample second data of the wordline, a second group of the groups of memory cells of a second sub-block of the sub-blocks; concurrently reading the first data from the first group and the second data from the second group of the groups of memory cells; and performing an error check of the wordline using the first data and the second data.

A system might include a first writing device and a second writing device. The first writing device might write first data to an array of memory cells in response to a first clock cycle of a clock signal. The write of the first data exceeds one clock cycle of the clock signal. The second writing device is in parallel with the first writing device. The second writing device might write second data to the array of memory cells in response to a second clock cycle of the clock signal. The second clock cycle follows the first clock cycle and the write of the second data exceeds one clock cycle of the clock signal.

A system might include a first writing device and a second writing device. The first writing device might write first data to an array of memory cells in response to a first clock cycle of a clock signal. The write of the first data exceeds one clock cycle of the clock signal. The second writing device is in parallel with the first writing device. The second writing device might write second data to the array of memory cells in response to a second clock cycle of the clock signal. The second clock cycle follows the first clock cycle and the write of the second data exceeds one clock cycle of the clock signal.

In some embodiments, an in-memory-computing SRAM macro based on capacitive-coupling computing (C3) (which is referred to herein as “C3SRAM”) is provided. In some embodiments, a C3SRAM macro can support array-level fully parallel computation, multi-bit outputs, and configurable multi-bit inputs. The macro can include circuits embedded in bitcells and peripherals to perform hardware acceleration for neural networks with binarized weights and activations in some embodiments. In some embodiments, the macro utilizes analog-mixed-signal capacitive-coupling computing to evaluate the main computations of binary neural networks, binary-multiply-and-accumulate operations. Without needing to access the stored weights by individual row, the macro can assert all of its rows simultaneously and form an analog voltage at the read bitline node through capacitive voltage division, in some embodiments. With one analog-to-digital converter (ADC) per column, the macro cab realize fully parallel vector-matrix multiplication in a single cycle in accordance with some embodiments.

A semiconductor apparatus includes a command decoding circuit and an enable signal generation circuit. The command decoding circuit generates an operation code and a strobe pulse based on a command signal and a clock signal. The enable signal generation circuit generates a seed signal based on the operation code and the strobe pulse and generates an enable signal by shifting the seed signal. The enable signal generation circuit generates a plurality of guard keys based on a plurality of operation codes and the strobe pulse and prevents the generation of the enable signal for a predetermined time when the plurality of guard keys are not sequentially enabled.