A memory system includes memory chips connected to each other. Each of the memory chips includes a memory array, a read/write data strobe pin, a look-up table storage device, a chip number identification circuit, and a control logic circuit. The memory array stores data. The read/write data strobe pin is connected to read/write data strobe pins of other memory chips. The look-up table storage device stores a plurality of trimming shift values related to a number of chip connections in advance. The chip number identification circuit identifies a current number of chip connections according to a state information, and finds a selected trimming shift value from the look-up table storage device. The control logic circuit transmits a data signal in response to a clock signal, and adjusts a setup hold time between the clock signal and the data signal according to the selected trimming shift value.

A memory system includes memory chips connected to each other. Each of the memory chips includes a memory array, a read/write data strobe pin, a look-up table storage device, a chip number identification circuit, and a control logic circuit. The memory array stores data. The read/write data strobe pin is connected to read/write data strobe pins of other memory chips. The look-up table storage device stores a plurality of trimming shift values related to a number of chip connections in advance. The chip number identification circuit identifies a current number of chip connections according to a state information, and finds a selected trimming shift value from the look-up table storage device. The control logic circuit transmits a data signal in response to a clock signal, and adjusts a setup hold time between the clock signal and the data signal according to the selected trimming shift value.

One aspect of this description relates to a memory array. The memory array includes a plurality of N-stack pass gates, a plurality of enable lines, a plurality of NMOS stacks, a plurality of word lines, and a matrix of resistive elements. Each N-stack pass gate includes a stage-1 PMOS core device and a stage-N PMOS core device in series. Each stage-1 PMOS is coupled to a voltage supply. Each enable line drives a stack pass gate. Each N-stack selector includes a plurality of NMOS stacks. Each NMOS stack includes a stage-1 NMOS core device and a stage-N NMOS core device in series. Each stage-1 NMOS core device is coupled to a ground rail. Each word line is driving a stack selector. Each resistive element is coupled between a stack pass gate and a stack selector. Each voltage supply is greater than a breakdown voltage for each of the core devices.

A memory system includes semiconductor memory devices and a control device. Each of the semiconductor memory devices includes a first pad to which a first signal is input, a second pad to which a second signal is input, a third pad to which a third signal is input, a memory cell array, a sense amplifier, and a data register. In a first mode, after the first signal is switched, a command set instructing a data out operation is input via the second pad. In a second mode, after the first signal is switched, the command is input via at least the third pad. The control device executes a first operation assigning different addresses to the respective semiconductor memory devices and a second operation causing the modes of the respective semiconductor memory devices to be switched from the first to the second mode.

A memory system includes semiconductor memory devices and a control device. Each of the semiconductor memory devices includes a first pad to which a first signal is input, a second pad to which a second signal is input, a third pad to which a third signal is input, a memory cell array, a sense amplifier, and a data register. In a first mode, after the first signal is switched, a command set instructing a data out operation is input via the second pad. In a second mode, after the first signal is switched, the command is input via at least the third pad. The control device executes a first operation assigning different addresses to the respective semiconductor memory devices and a second operation causing the modes of the respective semiconductor memory devices to be switched from the first to the second mode.

A semiconductor apparatus includes a command address control circuit. The command address control circuit is configured to receive a row command address signal and a column command address signal, and is configured to selectively invert the row command address signal and the column command address signal based on a logic level of at least one bit of the row command address signal.

A semiconductor apparatus includes a command address control circuit. The command address control circuit is configured to receive a row command address signal and a column command address signal, and is configured to selectively invert the row command address signal and the column command address signal based on a logic level of at least one bit of the row command address signal.

A memory device includes a command interface configured to receive a command from a host device via multiple command address bits. The memory device also includes a merged command decoder configured to receive the command and to determine whether the command matches a bit pattern corresponding to multiple command types. The merged command decoder is also configured to, in response to the command matching the bit pattern, asserting a latch signal. The memory device also includes a latch configured to capture the multiple command address bits based at least in part on assertion of the latch signal.

Systems and methods for gating, via clock gating circuitry, a clock signal based at least in part on a mode register value indicative of synchronization of a command address signal with the clock signal when the mode register value indicates synchronization of the command address signal with the clock signal has not occurred. The clock gating circuitry is configured to, gate the clock signal based at least in part on the mode register value and a chip select signal value when the mode register value indicates synchronization of the command address signal with the clock signal has occurred.

The present disclosure includes apparatuses and methods related to memory topologies. An apparatus may include a first plurality of clam-shell paired memory devices arranged in a star connection topology, each clam-shelled pair of the first plurality of memory devices being coupled by a respective matched branch to a first common command address signal trace. The apparatus may include a second plurality of memory devices coupled to a second common command address signal trace.