Numerous embodiments are disclosed for splitting an array of non-volatile memory cells in an analog neural memory in a deep learning artificial neural network into multiple parts. Each part of the array interacts with certain circuitry dedicated to that part and with other circuitry that is shared with one or more other parts of the array.

A security circuit includes a decoder configured to receive input data and output a decoding signal in response to the input data, a first encoder configured to output one of first phenotypes corresponding to any one among integers in N-decimal (N is a natural number of 1 or more) as a first encoding value in response to the decoding signal, a second encoder configured to output one of second phenotypes corresponding to any one among integers in N-decimal as a second encoding value in response to the decoding signal, and a gate module circuit configured to generate output data by performing a logic operation on the first encoding value and the second encoding value.

A security circuit includes a decoder configured to receive input data and output a decoding signal in response to the input data, a first encoder configured to output one of first phenotypes corresponding to any one among integers in N-decimal (N is a natural number of 1 or more) as a first encoding value in response to the decoding signal, a second encoder configured to output one of second phenotypes corresponding to any one among integers in N-decimal as a second encoding value in response to the decoding signal, and a gate module circuit configured to generate output data by performing a logic operation on the first encoding value and the second encoding value.

An electronic device includes first to n-th cells (‘n’ is an integer of 2 or more) that receive spatial-temporal input signals that indicate an event unit in a time window, a summation circuit that sums first to n-th cell signals recorded in the first to n-th cells for each of first to m-th unit times (‘m’ is an integer of 2 or more) dividing the time window to generate first to m-th summation signals, and an encoding circuit that compares each of the first to m-th summation signals with a threshold value to encode the spatial-temporal input signals into a code of the event unit.

A memory device includes a first memory array, a first isolation cell abutting a first side of the first memory array, a first edge cell array abutting a second side, opposite to the first side, of the first memory array, a second memory array arranged at a first side, opposite to the first memory array, of the first isolation cell, a second edge cell array, and multiple first word lines passing through the first edge cell array, the first memory array and being terminated at the first isolation cell. A first width of the first isolation cell is different from a second width of the first edge cell array. The second memory array is sandwiched between the second edge cell array and the first isolation cell.

A pseudo dual port memory device in which an operating speed is improved and stability is increased is provided. The pseudo dual port memory device may include a memory cell, a pair of bit lines connected to the memory cell, a write driver, a sense amp, and a column multiplexer which is connected to the bit lines, receives a write multiplexer control signal and a read multiplexer control signal, connects the bit lines to the write driver in response to the write multiplexer control signal, and connects the bit lines to the sense amp in response to the read multiplexer control signal. A precharge control signal generation circuit which is connected to the column multiplexer may generate a precharge control signal on the basis of the read and write multiplexer control signals, and a bit line precharge circuit may precharge the bit lines based on the precharge control signal.

Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address decoder circuit coupled to first and second select lines, a polarity line, and an access line. The first select line is configured to provide a first voltage, the second select line is configured to provide a second voltage, and the polarity line is configured to provide a polarity signal. The address decoder circuit is configured to receive address information and further configured to couple the access line to the first select line responsive to the address information having a combination of logic levels and the polarity signal having a first logic level and further configured to couple the access line to the second select line responsive to the address information having the combination of logic levels and the polarity signal having a second logic level.

A multi-level signal receiver includes a data sampler having (M−1) sense amplifiers therein, which are configured to compare a multi-level signal having one of M voltage levels with (M−1) reference voltages, to thereby generate (M−1) comparison signals. The data sampler is further configured to generate a target data signal including N bits, where M is an integer greater than two and N is an integer greater than one. An equalization controller is provided, which is configured to train the (M−1) sense amplifiers by: (i) adjusting at least one of (M−1) voltage intervals during a first training mode, and (ii) adjusting levels of the (M−1) reference voltages during a second training mode, based on equalized values of the (M−1) comparison signals, where each of the (M−1) voltage intervals represents a difference between two adjacent voltage levels from among the M voltage levels.

There are provided a volatile memory device, and an operating method. The volatile memory device includes: a plurality of memory cells arranged in rows and columns and structured to store data; word lines; bit lines; a row decoder; a column decoder; and a control logic coupled to communicate with the row and column decoders and configured to, in an active period, provide the row decoder with a first command, and provide the column decoder with a second command, wherein the row decoder is further configured to: apply a first word line voltage higher than a ground voltage to a selected word line, from when the first command is provided; and for a duration over which the row decoder is activated, apply either a second word line voltage lower than the first word line voltage to the selected word line or no voltage to the selected word line.

There are provided a volatile memory device, and an operating method. The volatile memory device includes: a plurality of memory cells arranged in rows and columns and structured to store data; word lines; bit lines; a row decoder; a column decoder; and a control logic coupled to communicate with the row and column decoders and configured to, in an active period, provide the row decoder with a first command, and provide the column decoder with a second command, wherein the row decoder is further configured to: apply a first word line voltage higher than a ground voltage to a selected word line, from when the first command is provided; and for a duration over which the row decoder is activated, apply either a second word line voltage lower than the first word line voltage to the selected word line or no voltage to the selected word line.