Systems, apparatuses and methods may provide for technology that sends a first command to a NAND die, sends first address information to the NAND die, and sends a second command to the NAND die, wherein the first command and the second command define a first command sequence and wherein the first address information signal a beginning of a first asynchronous read request from a first plurality of planes. In one example, the technology also sends a second command sequence and second address information to the NAND die wherein the second command sequence signals an end of the first asynchronous read request.

A semiconductor memory device includes a memory chip. The memory chip includes a first region including a plurality of first memory cells and second memory cells, a second region different from the first region, a plurality of first word lines stacked apart from each other in a first direction in the first and second regions, a first pillar including a first semiconductor layer extending through the first word lines, and a first insulator layer provided between the first semiconductor layer and the first word lines, in the first region, the first memory cells being located at intersections of the first pillar with the first word lines, a first bonding pad in the second region, and a first transistor between the first word lines and the first bonding pad, and connected between one of the first word lines and the first bonding pad, in the second region.

A semiconductor device is provided which includes: a first group including a plurality of first memory blocks; a second group including a plurality of second memory blocks; a first common source line connected to the first group; a second common source line connected to the second group; a source line voltage supplying circuit supplying a source line voltage; a first switch controlling a connection between the first common source line and the source line voltage supplying circuit; and a second switch controlling a connection between the second common source line and the source line voltage supplying circuit. When one first memory block among the plurality of first memory blocks of the first group is selected, the first switch may be turned on, and the second switch may be turned off.

A semiconductor memory device includes memory cell arrays including a first memory cell and a first word line connected to the first memory cell, a first wiring electrically connected to the first word lines corresponding to the memory cell arrays, a driver circuit electrically connected to the first wiring, second wirings electrically connected to the first wiring via the driver circuit, a voltage generation circuit including output terminals disposed corresponding to the second wirings, and first circuits disposed corresponding to the memory cell arrays. The voltage generation circuit is electrically connected to the first word lines via a first current path including the second wirings, the driver circuit, and the first wiring. The voltage generation circuit is electrically connected to the first word lines via a second current path including the second wirings and the first circuits and without including the driver circuit.

A memory includes: a plurality of row lines; a plurality of column lines; and a plurality of memory cells each of which is coupled to one row line among the row lines and one column line among the column lines, wherein memory cells corresponding to a row line which is selected based on a row address among the row lines are simultaneously activated, and data are read from memory cells corresponding to column lines which are selected based on a column address among the activated memory cells, and the selected column lines are not adjacent to each other.

A hybrid memory system provides rapid, persistent byte-addressable and block-addressable memory access to a host computer system by providing direct access to a both a volatile byte-addressable memory and a volatile block-addressable memory via the same parallel memory interface. The hybrid memory system also has at least a non-volatile block-addressable memory that allows the system to persist data even through a power-loss state. The hybrid memory system can copy and move data between any of the memories using local memory controllers to free up host system resources for other tasks.

A semiconductor device includes a level conversion circuit. The level conversion circuit includes a first transistor, a second transistor, a current limiting element, and a voltage adjusting circuit. The first transistor includes a gate connected to an input node. A signal corresponding to a first power supply voltage is input to the input node. The second transistor has a source connected to a drain of the first transistor, a drain connected to a second power supply voltage that is higher than the first power supply voltage, and a gate connected to a first node. The current limiting element is electrically connected between the first node and an output node. The voltage adjusting circuit adjusts a voltage of the first node in accordance with the signal input to the input node.

An embodiment of a memory device may include a full block memory array of a lower tile of 3D NAND string memory cells, a full block memory array of an upper tile of 3D NAND string memory cells, a first portion of a string driver circuit coupled to the full block memory array of the lower tile, a second portion of the string driver circuit coupled to the full block memory array of the upper tile, a first split block memory array of the lower tile coupled to the first portion of the string driver circuit, and a second split block memory array of the upper tile coupled to the second portion of the string driver circuit. Other embodiments are disclosed and claimed.

A solid-state storage drive and a solid-state storage drive control method are provided. The solid-state storage drive includes a controller, a selector, and N NAND flash memory chips, where N is an integer greater than 1. The controller is configured to output a plurality of gating signals to the selector. The plurality of gating signals indicate M of the N NAND flash memory chips, where M is an integer greater than or equal to 1 and less than or equal to N. The selector is configured to select, based on the plurality of gating signals, the M NAND flash memory chips to perform data transmission. This improves an interface rate of the solid-state storage drive, so that performance requirements of a high interface rate and a high storage capacity of the solid-state storage drive can be satisfied.

The present disclosure provides a content addressable memory (CAM) for repairing firmware of multi-plane read operations in a flash memory device. The CAM comprises a set of CAM registers configured to store a mapping table. The mapping table comprises a plurality of old addresses, each old address corresponding to a new address. The CAM also comprises N comparators coupling to the set of CAM registers, and configured to compare the old addresses with N input signals for performing the multi-plane read operations on N memory planes, wherein N is an integer greater than 1. The CAM further comprises N multiplexers coupling to the N comparators respectively and to the set of CAM registers, and configured to generate N output signals for the multi-plane read operations. At least one of the N output signals comprises the new address according to the mapping table and a comparison output by the comparators.