A memory device includes a memory cell array, a row address decoder configured to generate a plurality of main word line driving signals and a plurality of sub word line driving signals, based on an odd signal representing that a main word line driving signal driving an odd word line is activated, generate a plurality of encoded sub word line driving signals used for driving a target word line by outputting the plurality of sub word line driving signals in a first order, and, based on an even signal representing that a main word line driving signal driving an even word line is activated, generate the plurality of encoded sub word line driving signals by outputting the plurality of sub word line driving signals in a second order, and a word line driving circuit configured to drive the target word line at a first voltage level or a second voltage level.

A sub-word-line driver and semiconductor memory devices including the same are provided. The sub-word-line driver may include a word line pull-up transistor, a word line pull-down transistor, and a keeping transistor configured to maintain a word line at a specified voltage level. The sub-word-line driver may include a peripheral active region on a substrate, a first peripheral gate electrode that corresponds to a gate node of the word line pull-down transistor on the peripheral active region, a second peripheral gate electrode that corresponds to a gate node of the keeping transistor on the peripheral active region, and a first lower contact coupled to a first region of the peripheral active region. A first (VBB) voltage from the first region may be supplied to a source node of the keeping transistor.

A memory device includes a page made up of plural memory cells arranged in a column on a substrate, and a page write operation is performed to hold positive hole groups generated by an impact ionization phenomenon, in a channel semiconductor layer by controlling voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each memory cell contained in the page and a page erase operation is performed to remove the positive hole groups out of the channel semiconductor layer by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region. The first impurity layer of the memory cell is connected with a source line, the second impurity layer is connected with a bit line, one of the first gate conductor layer and the second gate conductor layer is connected with a word line, and another is connected with a drive control line, and the bit line is connected to a sense amplifier circuit via a switch circuit. During a page read operation, page data of a memory cell group selected by the word line is read into a sense amplifier circuit concurrently with a memory cell refresh operation for forming positive hole groups.

A nonvolatile memory device comprises a first semiconductor layer including, an upper substrate, and a memory cell array in which a plurality of word lines on the upper substrate extend in a first direction and a plurality of bit lines extend in a second direction. The nonvolatile memory device comprises a second semiconductor layer under the first semiconductor layer in a third direction perpendicular to the first and second directions, the second semiconductor layer including, a lower substrate, and a substrate control circuit on the lower substrate and configured to output a bias voltage to the upper substrate. The second semiconductor layer is divided into first through fourth regions, each of the first through fourth regions having an identical area, and the substrate control circuit overlaps at least a portion of the first through fourth regions in the third direction.

A nonvolatile memory device comprises a first semiconductor layer including, an upper substrate, and a memory cell array in which a plurality of word lines on the upper substrate extend in a first direction and a plurality of bit lines extend in a second direction. The nonvolatile memory device comprises a second semiconductor layer under the first semiconductor layer in a third direction perpendicular to the first and second directions, the second semiconductor layer including, a lower substrate, and a substrate control circuit on the lower substrate and configured to output a bias voltage to the upper substrate. The second semiconductor layer is divided into first through fourth regions, each of the first through fourth regions having an identical area, and the substrate control circuit overlaps at least a portion of the first through fourth regions in the third direction.

A memory device includes first to nth decks respectively coupled to first to nth row lines which are stacked over a substrate in a vertical direction perpendicular to a surface of the substrate, n being a positive integer, a first connection structure extending from the substrate in the vertical direction to be coupled to the first row line, even-numbered connection structures extending from the substrate in the vertical direction and respectively coupled to ends of even-numbered row lines among the second to nth row lines, and odd-numbered connection structures extending from the substrate in the vertical direction and respectively coupled to ends of odd-numbered row lines among the second to nth row lines. The even-numbered connection structures are spaced apart from the odd-numbered connection structures with the first row line and the first connection structure that are interposed between the even-numbered connection structures and the odd-numbered connection structures.

Electrically conductive line side-by-side running distance equalization and related apparatuses and systems. An apparatus includes a first sense amplifier, a second sense amplifier, a first pair of lines, and a second pair of lines. The first sense amplifier includes a first pull-up sense amplifier and a first pull-down sense amplifier. The first pair of lines electrically connects a first pull-up sense amplifier of the first sense amplifier to a first pull-down sense amplifier of the first sense amplifier. The second pair of lines electrically connects the second pull-up sense amplifier to the second pull-down sense amplifier. Parallel running distances between lines of the first pair of lines and the second pair of lines are equalized by a wiring twist of the first pair of lines and three wiring twists of the second pair of lines.

Subject matter disclosed herein relates to an integrated circuit device having a socket interconnect region for connecting a plurality of conductive lines at a first vertical level to interconnect structures formed at a second vertical level different from the first vertical level. The conductive lines include a plurality of contacted lines that are vertically connected to the interconnect structures at the socket interconnect region, a plurality of terminating lines terminating at the socket interconnect region, and a plurality of pass-through lines that pass through the socket interconnect region without being vertically connected and without being terminated at the socket interconnect region.

Memory systems having flying bitlines for improved burst mode read operations and related methods are provided. A memory system comprises a memory array including a first set of memory cells coupled to a first inner wordline and a second set of memory cells coupled to a first outer wordline. The memory system includes a control unit configured to generate control signals for simultaneously: asserting a first wordline signal on the first inner wordline coupled to each of a plurality of inner bitlines, and asserting a second wordline signal on the first outer wordline coupled to each of a plurality of outer bitlines, where each of the plurality of outer bitlines includes a first portion configured to fly over or fly under a corresponding inner bitline, and outputting data from each of the first set of memory cells and the second set of memory cells as part of a burst.

Memory systems with burst mode having logic gates as sense elements and related methods are provided. A memory system comprises a memory array including a first set of memory cells coupled to a first wordline, a second set of memory cells coupled to a second wordline, and a plurality of sense elements, not including any sense amplifiers. The control unit is configured to generate control signals for: in response to a burst mode read request, simultaneously: (1) asserting a first wordline signal on the first wordline coupled to each of a plurality of first set of bitlines, and (2) asserting a second wordline signal on the second wordline coupled to each of a plurality of second set of bitlines, and as part of a burst, outputting data corresponding to a subset of each of the first set of memory cells and the second set of memory cells.