Methods, systems, and devices for a differential write operation are described. The operations described herein may be used to alter a portion of a program file from a first state to a second state. For example, a file (e.g., a patch file) that is associated with a signature may be received at a memory device. Based on an authentication process, the file may be used to alter the program file to the second state. In some examples, the program file may be altered to the second state using a buffer of the memory device. A host system may transmit a file that includes the difference between the first state and the second state. A signature may be associated with the file and may be used to authenticate the file.

A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.

The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a memory array including a plurality of memory cells, each memory cell having an impedance that varies in accordance with a respective data value stored therein; and a tracking memory cell having an impedance based on a tracking data value stored therein; and a read circuit coupled to the memory array, the read circuit configured to determine an impedance of a selected memory cells with respect to the impedance of the tracking memory cell; read a data value stored within the selected memory cell based upon a voltage change of a signal node voltage corresponding to the impedance of the selected memory cell.

A storage array includes a read bit line, a ground, a read bit line switch of the read bit line, and a plurality of storage circuits. Each storage circuit includes a storage unit configured to store data and a read circuit configured to read data from the storage unit. A data input end of the read circuit is connected to a data output end of the storage unit, to read data from the storage circuit, and a data output end of the read circuit is connected to the read bit line, to output the read data to the read bit line. There is at least one PMOS transistor in an electric leakage path from a power supply to the read bit line in the read circuit, to suppress a leakage current in the read circuit.

The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a memory array including a plurality of memory cells, each memory cell having an impedance that varies in accordance with a respective data value stored therein; and a tracking memory cell having an impedance based on a tracking data value stored therein; and a read circuit coupled to the memory array, the read circuit configured to determine an impedance of a selected memory cells with respect to the impedance of the tracking memory cell; read a data value stored within the selected memory cell based upon a voltage change of a signal node voltage corresponding to the impedance of the selected memory cell.

Various implementations described herein refer to a device having an address bus that provides multi-port addresses from multiple ports including a first address from a first port and a second address from a second port. The device may have column contention-detection circuitry that receives the multi-port addresses from the address bus, compares the first address from the first port with the second address from the second port and provides a contention adjustment signal based on the comparison between the first address and the second address. The device may have bitline collision circuitry that receives the contention adjustment signal, senses wire-to-wire variation related to bitline coupling effects and provides a bitline collision signal based on sensing the bitline coupling effects.

A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.

Embodiments of the present invention provide a storage cell and a data read/write method and storage array thereof. The storage cell includes a bit line, a tunnel junction, and four access transistors. Each access transistor includes at least an active region. The active region includes a source. The sources of the access transistors are all electrically connected to a first end of the tunnel junction. A second end of the tunnel junction is electrically connected to the bit line, and the bit line extends along a first direction. The active regions of the access transistors are isolated from one another. Long-side extension directions of the active regions of the access transistors are the same, and a first angle θ is formed between the long-side extension directions of the active regions and the first direction; wherein θ is a non-right angle.

A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.

A memory is provided that is configured to practice two different modes of read operation, such as both a normal read operation and a burst-mode read operation. In one example, the memory is a pseudo-dual-port memory. The memory may include an address comparator to perform a time-division multiplexing to first compare a read address to a stored address and then to compare a write address to the stored address.