Memory array circuits including word line circuits providing word line signal stability are disclosed. In a memory access operation, the states of word line signals on word lines in the memory rows of the memory array may be based on the states of word line latches during a first clock state of a latch clock signal. The word line latches receive address decode signals generated from a decoded memory address. An inverted delay clock circuit generates a clock pulse from the latch clock signal. The word line latches store the address decode signals during the clock pulse and generate word line signals based on the stored address decode signals. The memory address is received from an address bus. Pass-through address capture latches maximize time available to a decoder for decoding the memory address and word line latches reduce fluctuations in the address signal being propagated to the word line signals.

Methods, systems, and apparatuses for managing clock signals at a memory device are described. A memory device or other component of a memory module or electronic system may offset a received clock signal. For example, the memory device may receive a clock signal that has a nominal speed or frequency of operation for a system, and the memory device may adjust or offset the clock signal based on other operating factors, such as the speed or frequency of other signals, physical constraints, indications received from a host device, or the like. A clock offset value may be based on propagation of, for example, command/address signaling. In some examples, a memory module may include a registering clock driver (RCD), hub, or local controller that may manage or coordinate clock offsets among or between various memory devices on the module. Clock offset values may be programmed to a mode register or registers.

Methods, systems, and apparatuses for managing clock signals at a memory device are described. A memory device or other component of a memory module or electronic system may offset a received clock signal. For example, the memory device may receive a clock signal that has a nominal speed or frequency of operation for a system, and the memory device may adjust or offset the clock signal based on other operating factors, such as the speed or frequency of other signals, physical constraints, indications received from a host device, or the like. A clock offset value may be based on propagation of, for example, command/address signaling. In some examples, a memory module may include a registering clock driver (RCD), hub, or local controller that may manage or coordinate clock offsets among or between various memory devices on the module. Clock offset values may be programmed to a mode register or registers.

A circuit includes a plurality of registers, each register including SRAM cells, a read port configured to receive a read address, a write port configured to receive a write address, a selection circuit, a latch circuit, and a decoder coupled in series between the read and write ports and the plurality of registers, and a control circuit. Responsive to a clock signal and read and write enable signals, the control circuit causes the selection circuit, the latch circuit, and the decoder to select a first register of the plurality of registers in a read operation based on the read address, and select a second register of the plurality of registers in a write operation based on the write address.

A memory system includes a host circuit and a memory circuit. The host circuit controls a bandwidth of a command-address signal based on data driving cycle information. The memory circuit performs an input/output operation based on the command-address signal.

An electronic device includes first to n-th cells (‘n’ is an integer of 2 or more) that receive spatial-temporal input signals that indicate an event unit in a time window, a summation circuit that sums first to n-th cell signals recorded in the first to n-th cells for each of first to m-th unit times (‘m’ is an integer of 2 or more) dividing the time window to generate first to m-th summation signals, and an encoding circuit that compares each of the first to m-th summation signals with a threshold value to encode the spatial-temporal input signals into a code of the event unit.

An operation method of a memory device, having a plurality of memory cells, includes receiving a partial write command, which includes a partial write enable signal (PWE) and a plurality of mask signals, during a command/address input interval. A data strobe signal is received through a data strobe line after receiving the partial write command Data is received through a plurality of data lines in synchronization with the data strobe signal during a data input interval. A part of the data is stored in the plurality of memory cells based on the plurality of mask signals, in response to the partial write enable signal, during a data write interval.

An operation method of a memory device, having a plurality of memory cells, includes receiving a partial write command, which includes a partial write enable signal (PWE) and a plurality of mask signals, during a command/address input interval. A data strobe signal is received through a data strobe line after receiving the partial write command Data is received through a plurality of data lines in synchronization with the data strobe signal during a data input interval. A part of the data is stored in the plurality of memory cells based on the plurality of mask signals, in response to the partial write enable signal, during a data write interval.

A system and method for optimizing a memory sub-system to compensate for memory device degradation. An example system including a memory controller operatively coupled with a memory device and configured to perform operations comprising: updating a setting of the memory device, wherein the setting changes a duty cycle of a signal of the memory device and comprises a first value for a first configuration and comprises a second value for a second configuration; storing error data that indicates errors when using the first configuration and errors when using the second configuration; determining a value for the setting based on the error data, wherein the determined value minimizes errors associated with the memory device; and storing the determined value for the setting of the memory device.

A system and method for optimizing a memory sub-system to compensate for memory device degradation. An example system including a memory controller operatively coupled with a memory device and configured to perform operations comprising: updating a setting of the memory device, wherein the setting changes a duty cycle of a signal of the memory device and comprises a first value for a first configuration and comprises a second value for a second configuration; storing error data that indicates errors when using the first configuration and errors when using the second configuration; determining a value for the setting based on the error data, wherein the determined value minimizes errors associated with the memory device; and storing the determined value for the setting of the memory device.