A memory device having a plurality sections of memory cells, such as ferroelectric memory cells (hybrid RAM (HRAM) cells) may provide for concurrent access to memory cells within independent sections of the memory device. A first memory cell may be activated, and it may be determined that a second memory cell is independent of the first memory cell. If the second memory cell is independent of the first memory cell, the second memory cell may be activated prior to the conclusion of operations at the first memory cell. Latching hardware at memory sections may latch addresses at the memory sections in order to allow a new address to be provided to a different section to access the second memory cell.

An integrated circuit includes a driving circuit and an enable control circuit. The driving circuit is configured to perform a setup operation based on a first driving current and perform a preset operation, using different driving currents, based on a first enable signal and a second enable signal. The enable control circuit is configured to generate the first and second enable signals.

An integrated circuit includes a driving circuit and an enable control circuit. The driving circuit is configured to perform a setup operation based on a first driving current and perform a preset operation, using different driving currents, based on a first enable signal and a second enable signal. The enable control circuit is configured to generate the first and second enable signals.

A signal processing circuit includes a first signal latch circuit, a second signal latch circuit, and a decoder. The first signal latch circuit receives a command address signal and is driven by an even clock; the second signal latch circuit receives the command address signal and is driven by an odd clock; and the decoder is connected to the first signal latch circuit and the second signal latch circuit, and outputs a control signal. Both the even clock and the odd clock have a frequency equal to that of a reference clock, and both the even clock and the odd clock have a rising edge aligned with a rising edge of the reference clock.

A signal processing circuit includes a first signal latch circuit, a second signal latch circuit, and a decoder. The first signal latch circuit receives a command address signal and is driven by an even clock; the second signal latch circuit receives the command address signal and is driven by an odd clock; and the decoder is connected to the first signal latch circuit and the second signal latch circuit, and outputs a control signal. Both the even clock and the odd clock have a frequency equal to that of a reference clock, and both the even clock and the odd clock have a rising edge aligned with a rising edge of the reference clock.

Disclosed are methods for reading data from a storage buffer. One such method may include retrieving a first set of data during a first period of time. The method may also include delaying data retrieval during a second period of time after the first period of time. The method may include outputting at least a portion of the first set of data during the first period of time and the second period of time. The first period of time is substantially similar to the second period of time.

Disclosed are methods for reading data from a storage buffer. One such method may include retrieving a first set of data during a first period of time. The method may also include delaying data retrieval during a second period of time after the first period of time. The method may include outputting at least a portion of the first set of data during the first period of time and the second period of time. The first period of time is substantially similar to the second period of time.

Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory controller is disclosed. The IC memory controller includes a first controller command/address (C/A) interface to transmit first and second read commands for first and second read data to a first memory C/A interface of a first bank group of memory. A second command/address (C/A) interface transmits third and fourth read commands for third and fourth read data to a second memory C/A interface of a second bank group of memory. Receiver circuitry receives the first and second read data via a first data link interface and the third and fourth read data via the second data link interface. For a first operating mode, the first and second read data are received after respective first delays following transmission of the first and second read commands and at a first serialization ratio. For a second operating mode, the first and second read data are received after respective second and third delays following transmission of the first and second read commands. The second and third delays are different from the first delays and from each other. The first and second data are received at a second serialization ratio that is different than the first serialization ratio.

Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory controller is disclosed. The IC memory controller includes a first controller command/address (C/A) interface to transmit first and second read commands for first and second read data to a first memory C/A interface of a first bank group of memory. A second command/address (C/A) interface transmits third and fourth read commands for third and fourth read data to a second memory C/A interface of a second bank group of memory. Receiver circuitry receives the first and second read data via a first data link interface and the third and fourth read data via the second data link interface. For a first operating mode, the first and second read data are received after respective first delays following transmission of the first and second read commands and at a first serialization ratio. For a second operating mode, the first and second read data are received after respective second and third delays following transmission of the first and second read commands. The second and third delays are different from the first delays and from each other. The first and second data are received at a second serialization ratio that is different than the first serialization ratio.

A memory system includes a nonvolatile memory configured to execute one of a plurality of read operations, including a first read operation and a second read operation, and a memory controller configured to issue a read command to the nonvolatile memory to cause the nonvolatile memory to execute one of the plurality of read operations. The memory controller is configured to receive a read request, estimate a reliability level of a result of a read operation to be executed by the nonvolatile memory to read data from a physical address specified in the read request, select one of the first and second read operations to be executed first in a read sequence corresponding to the read request by the nonvolatile memory based on the estimated reliability level, and instruct the nonvolatile memory to execute the selected read operation.