Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first non-volatile memory with first data from a first data lane that includes a first volatile memory device, and filling a second plurality of pages of the first non-volatile memory device with second data from a second data lane that includes a second volatile memory device. In certain examples, the first plurality of pages does not include data from the second data lane.

A memory system is disclosed that includes a first FPGA controller coupled to a first SSD cluster, a first DDR4 DIMM and a second DDR4 DIMM. A second FPGA controller is coupled to a second SSD cluster, the first DDR4 DIMM and the second DDR4 DIMM, where the first and second FPGAs are operable to share access to the first and second DDR4 DIMMs and provide connectivity to a plurality of network resources. The dual-port design enables the use of existing SDRAM, MRAM and RRAM chips at low speed rates to reach DDR4 2.0 speed DIMM devices. The dual-port DDR4 DIMM comprises 1-to-2 data buffer splitters and a DDR3 or DDR2 to DDR4 bus adaptation/termination/relaying circuits to increase (e.g., double or quadruple) the chip speed of SDRAM, MRAM, and RRAM chips.

Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.

A system includes a bus, at least one processor coupled to the bus, and a storage device coupled to the bus. The storage device includes storage class memory, a buffer; and a controller. The controller is configured to receive an instruction to provide data to the bus. Responsive to receiving the instruction to provide data to the bus, the controller is configured to retrieve data from the storage class memory, update the buffer to represent the data retrieved from the storage class memory, and output, at the bus, an indication that data responsive to the instruction to provide data to the bus is available at the buffer. The at least one processor is configured to refrain from modifying local data corresponding to the instruction to provide data to the bus after the controller receives the instruction to provide data to the bus and before the controller outputs the indication.

A memory control circuit unit, a memory storage device and a signal receiving method. In one exemplary embodiment, a memory interface circuit of the memory control circuit unit receives a first signal from a volatile memory and adjusts a voltage value of the first signal to a voltage range in response to an internal impedance of the memory interface circuit, where a central value of the voltage range is not equal to a default voltage value, and the default voltage value is one half a sum of a voltage value of a supply voltage of the memory interface circuit and a voltage value of a reference ground voltage. In addition, the memory interface circuit further generates an input signal according to a voltage correspondence between the first signal and an internal reference voltage.

A system, method and apparatus to provide data recovery capabilities during an emergency power failure event. A non-volatile storage system is provided to be coupled with a host computer system. The non-volatile storage system includes an embedded non-volatile memory array for persistently storing data and an embedded volatile memory array for temporarily storing the data before committing the data to the non-volatile memory array. The non-volatile storage system provides a normal operating data path transferring data from the volatile memory array to the non-volatile memory array during normal operating condition. The normal operating data path includes data processing blocks. The non-volatile storage system also provides an emergency data path for transferring data from the volatile memory array to the non-volatile memory array during an emergency power loss condition. The emergency data path excludes the data processing blocks.

Disclosed are fusion memory devices and methods of fabricating the same. The fusion memory device comprises a first memory device including a first substrate having active and inactive surfaces opposite to each other and a first memory cell circuit on the active surface of the first substrate, a non-memory device including a second substrate having active and inactive surfaces opposite to each other and a non-memory circuit on the active surface of the second substrate, the non-memory device being provided on the first memory device, and a second memory device on the inactive surface of the second substrate and including a second memory cell circuit different from the first memory cell circuit. The non-memory device lies between the first and second memory cell circuits and controls an electrical operation of each of the first and second memory cell circuits.

A memory device and an operating method thereof are provided. The memory device includes a first memory array, a first row decoder, a first column decoder, a second memory array, a second row decoder and a second column decoder. The first memory array and the second memory array are different type memories and formed in a single memory die of a wafer.

A method includes: providing a DDR interface between a host memory controller and a memory module; and providing a message interface between the host memory controller and the memory module. The memory module includes a non-volatile memory and a DRAM configured as a DRAM cache of the non-volatile memory. Data stored in the non-volatile memory of the memory module is asynchronously accessible by a non-volatile memory controller of the memory module, and data stored in the DRAM cache is directly and synchronously accessible by the host memory controller.

An electronic device includes: a magnetic first nonvolatile memory that has no movable element; a nonmagnetic second nonvolatile memory; and a processor. The processor is configured to execute processing including: stopping writing data onto the first nonvolatile memory but writing the data onto the second nonvolatile memory in response to determining, based on magnetic field information regarding a magnetic field around the electronic device, that the electronic device is on a magnetic field equal to or stronger than a reference magnetic field strength in writing the data onto the first nonvolatile memory; and writing the data of the second nonvolatile memory onto the first nonvolatile memory in response to determining, based on the magnetic field information, that the electronic device is not on the magnetic field and that the data is on the second nonvolatile memory.