An integrated circuit includes an artificial intelligence (AI) logic and an embedded memory coupled to the AI logic and connectable to an external processor. The embedded memory includes multiple storage cells and multiple reference units. One or more reference units in the memory are selected for memory access through configuration at chip packaging level by the external processor. The external processor may execute a self-test process to select or update the one or more reference units for memory access so that the error rate of memory is below a threshold. The self-test process may be performed, via a memory initialization controller in the memory, to test and reuse the reference cells in the memory at chip level. The embedded memory may be a STT-MRAM, SOT, OST MRAM, and/or MeRAM memory.

An integrated circuit includes an artificial intelligence (AI) logic and an embedded memory coupled to the AI logic and connectable to an external processor. The embedded memory includes multiple storage cells and multiple reference units. One or more reference units in the memory are selected for memory access through configuration at chip packaging level by the external processor. The external processor may execute a self-test process to select or update the one or more reference units for memory access so that the error rate of memory is below a threshold. The self-test process may be performed, via a memory initialization controller in the memory, to test and reuse the reference cells in the memory at chip level. The embedded memory may be a STT-MRAM, SOT, OST MRAM, and/or MeRAM memory.

The magnetoresistance effect device includes: a first port; a second port; a magnetoresistance effect element; a first signal line that is connected to the first port and applies a high frequency magnetic field to the magnetoresistance effect element; a second signal line that connects the second port and the magnetoresistance effect element to each other; and a direct current application terminal capable of being connected to a power supply that applies a direct current or a direct current voltage. The first signal line includes a magnetic field generator, which extends in a first direction, at a position in the lamination direction of the magnetoresistance effect element or an in-plane direction that is orthogonal to the lamination direction, and the magnetic field generator and the magnetoresistance effect element include an overlapping portion as viewed from the lamination direction in which the magnetic field generator is disposed, or the in-plane direction.

The magnetoresistance effect device includes: a first port; a second port; a magnetoresistance effect element; a first signal line that is connected to the first port and applies a high frequency magnetic field to the magnetoresistance effect element; a second signal line that connects the second port and the magnetoresistance effect element to each other; and a direct current application terminal capable of being connected to a power supply that applies a direct current or a direct current voltage. The first signal line includes a magnetic field generator, which extends in a first direction, at a position in the lamination direction of the magnetoresistance effect element or an in-plane direction that is orthogonal to the lamination direction, and the magnetic field generator and the magnetoresistance effect element include an overlapping portion as viewed from the lamination direction in which the magnetic field generator is disposed, or the in-plane direction.

A magnetic element is provided. The magnetic element includes a free magnetization layer having a surface area that is approximately 1,600 nm2 or less, the free magnetization layer including a magnetization state that is configured to be changed; an insulation layer coupled to the free magnetization layer, the insulation layer including a non-magnetic material; and a magnetization fixing layer coupled to the insulation layer opposite the free magnetization layer, the magnetization fixing layer including a fixed magnetization so as to be capable of serving as a reference of the free magnetization layer.

A method and apparatus determine an exchange stiffness of a free layer residing in a magnetic junction. The method includes performing spin torque ferromagnetic resonance (ST-FMR) measurements for the magnetic junction. The ST-FMR measurements indicate characteristic frequencies corresponding to spin wave modes in the free layer. The method also includes calculating the exchange stiffness of the free layer based upon the plurality of characteristic frequencies. In some embodiments, the magnetic junction resides on a wafer including other magnetic junctions for a device. The magnetic junctions may be arranged as a magnetic memory. The magnetic junction undergoing ST-FMR has a different aspect ratio than the magnetic junctions.

A method and apparatus determine an exchange stiffness of a free layer residing in a magnetic junction. The method includes performing spin torque ferromagnetic resonance (ST-FMR) measurements for the magnetic junction. The ST-FMR measurements indicate characteristic frequencies corresponding to spin wave modes in the free layer. The method also includes calculating the exchange stiffness of the free layer based upon the plurality of characteristic frequencies. In some embodiments, the magnetic junction resides on a wafer including other magnetic junctions for a device. The magnetic junctions may be arranged as a magnetic memory. The magnetic junction undergoing ST-FMR has a different aspect ratio than the magnetic junctions.

An integrated circuit includes an artificial intelligence (AI) logic and an embedded memory coupled to the AI logic and connectable to an external processor. The embedded memory includes multiple storage cells and multiple reference units. One or more reference units in the memory are selected for memory access through configuration at chip packaging level by the external processor. The external processor may execute a self-test process to select or update the one or more reference units for memory access so that the error rate of memory is below a threshold. The self-test process may be performed, via a memory initialization controller in the memory, to test and reuse the reference cells in the memory at chip level. The embedded memory may be a STT-MRAM, SOT, OST MRAM, and/or MeRAM memory.

An integrated circuit includes an artificial intelligence (AI) logic and an embedded memory coupled to the AI logic and connectable to an external processor. The embedded memory includes multiple storage cells and multiple reference units. One or more reference units in the memory are selected for memory access through configuration at chip packaging level by the external processor. The external processor may execute a self-test process to select or update the one or more reference units for memory access so that the error rate of memory is below a threshold. The self-test process may be performed, via a memory initialization controller in the memory, to test and reuse the reference cells in the memory at chip level. The embedded memory may be a STT-MRAM, SOT, OST MRAM, and/or MeRAM memory.

A magnetic element is provided. The magnetic element includes a free magnetization layer having a surface area that is approximately 1,600 nm2 or less, the free magnetization layer including a magnetization state that is configured to be changed; an insulation layer coupled to the free magnetization layer, the insulation layer including a non-magnetic material; and a magnetization fixing layer coupled to the insulation layer opposite the free magnetization layer, the magnetization fixing layer including a fixed magnetization so as to be capable of serving as a reference of the free magnetization layer.