G11C11/21

Tri-stable storage loops

A tri-stable storage loop useful in reciprocal quantum logic (RQL) gate circuits and systems has control and signal input lines. When alternating stable current storage states are induced in the storage loop by an alternating input provided to the control input line, provision of a positive SFQ pulse on the signal input line while the storage loop stores a positive current changes the storage loop from alternating between a positive-current state and a null-current state to alternating between a negative-current state and the null-current state, and provision of a negative SFQ pulse on the signal input line while the storage loop stores a negative current changes the storage loop from alternating between the negative-current state and the null-current state to alternating between the positive-current state and the null-current state.

FABRICATION OF AN SD CARD INSERTED ELECTRONIC OR A PLAIN IDENTIFICATION CARD
20180349752 · 2018-12-06 ·

An electronic or a plain identification card to hold an SD card in a unique way provided with a stored memory and a header for interfacing with an electronic port of a reader device is disclosed. The electronic identification card comprises a card body provided with a recess to hold the SD card with the help of an adhesive means, a plurality of contact connections to supply power when connected to a host, a plurality of protection layers at the top and bottom surface of the electronic identification card preventing any slippage of SD card. The recess can be provided at any location on the electronic or a plain identification card to incorporate an SD card used for identifying an intended holder of a device through the memory stored in the card.

FABRICATION OF AN SD CARD INSERTED ELECTRONIC OR A PLAIN IDENTIFICATION CARD
20180349752 · 2018-12-06 ·

An electronic or a plain identification card to hold an SD card in a unique way provided with a stored memory and a header for interfacing with an electronic port of a reader device is disclosed. The electronic identification card comprises a card body provided with a recess to hold the SD card with the help of an adhesive means, a plurality of contact connections to supply power when connected to a host, a plurality of protection layers at the top and bottom surface of the electronic identification card preventing any slippage of SD card. The recess can be provided at any location on the electronic or a plain identification card to incorporate an SD card used for identifying an intended holder of a device through the memory stored in the card.

Memory Cell And An Array Of Memory Cells

A memory cell includes a first electrode and a second electrode. A select device and a programmable device are in series with each other between the first and second electrodes. The select device is proximate and electrically coupled to the first electrode. The programmable device is proximate and electrically coupled to the second electrode. The programmable device includes a radially inner electrode having radially outer sidewalls. Ferroelectric material is radially outward of the outer sidewalls of the inner electrode. A radially outer electrode is radially outward of the ferroelectric material. One of the outer electrode or the inner electrode is electrically coupled to the select device. The other of the outer electrode and the inner electrode is electrically coupled to the second electrode. Arrays of memory cells are disclosed.

Access signal adjustment circuits and methods for memory cells in a cross-point array

Systems, integrated circuits, and methods to utilize access signals to facilitate memory operations in scaled arrays of memory elements are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and line driver. The line driver can be configured to access a resistive memory element in the cross-point array.

Memory cell and an array of memory cells

A memory cell includes a first electrode and a second electrode. A select device and a programmable device are in series with each other between the first and second electrodes. The select device is proximate and electrically coupled to the first electrode. The programmable device is proximate and electrically coupled to the second electrode. The programmable device includes a radially inner electrode having radially outer sidewalls. Ferroelectric material is radially outward of the outer sidewalls of the inner electrode. A radially outer electrode is radially outward of the ferroelectric material. One of the outer electrode or the inner electrode is electrically coupled to the select device. The other of the outer electrode and the inner electrode is electrically coupled to the second electrode. Arrays of memory cells are disclosed.

CIRCUITS AND TECHNIQUES TO COMPENSATE MEMORY ACCESS SIGNALS FOR VARIATIONS OF PARAMETERS IN MULTIPLE LAYERS OF MEMORY
20180226110 · 2018-08-09 ·

Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

CIRCUITS AND TECHNIQUES TO COMPENSATE MEMORY ACCESS SIGNALS FOR VARIATIONS OF PARAMETERS IN MULTIPLE LAYERS OF MEMORY
20180226110 · 2018-08-09 ·

Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

NANO SENSOR
20180217117 · 2018-08-02 ·

A device includes an upper metallic layer, a lower layer, and a nano sensor array positioned between the upper and lower layers to detect a presence of a gas, a chemical, or a biological object, wherein each sensor's electrical characteristic changes when encountering the gas, chemical or biological object.

Semiconductor Memory Having Both Volatile and Non-Volatile Functionality Comprising Resistive Change Material and Method of Operating
20180182460 · 2018-06-28 ·

A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.