A ferroelectric mechanical memory structure comprising a substrate, a MEMS switch element movable between a first position and at least one second position, the MEMS switch element comprising first and second electrodes, a layer of ferroelectric material positioned between the first and second electrodes so that upon application of voltage between the first and second electrodes the MEMS switch element moves between the first position and the second position, and a switch contact which contacts the first electrode only when the MEMS switch element is in the first position, wherein the ferroelectric material is selected so that the remanent strain within the layer of ferroelectric material is controlled by the history of the voltage potential applied to the ferroelectric material by the first and second electrodes, and wherein the remanent strain is sufficient to retain the MEMS switch element in the first or second position upon removal of the voltage.

A method of making a memory device comprising a base; a capacitor comprising a ferroelectric layer and at least two electrically conductive layers, the ferroelectric layer being located between the at least two electrically conductive layers; each of the at least two conductive layers being operatively connected to a current source; a cantilever attached to the base at first end and movable at a second end, the ferroelectric capacitor being mounted to the cantilever such that the second end of the cantilever moves a predetermined displacement upon application of a current to the ferroelectric layer which induces deformation of the ferroelectric layer thereby causing displacement of the cantilever which is operatively associated with a contact so that an electrical connection is enabled with the contact upon the predetermined displacement of the cantilever. The presence or absence of a connection forms two states of a memory cell.

A method of making a memory device comprising a base; a capacitor comprising a ferroelectric layer and at least two electrically conductive layers, the ferroelectric layer being located between the at least two electrically conductive layers; each of the at least two conductive layers being operatively connected to a current source; a cantilever attached to the base at first end and movable at a second end, the ferroelectric capacitor being mounted to the cantilever such that the second end of the cantilever moves a predetermined displacement upon application of a current to the ferroelectric layer which induces deformation of the ferroelectric layer thereby causing displacement of the cantilever which is operatively associated with a contact so that an electrical connection is enabled with the contact upon the predetermined displacement of the cantilever. The presence or absence of a connection forms two states of a memory cell.

A digital memory device includes a moveable element that is configured to move between a first stable position and a second stable position, where the moveable element comprises a first conducting area. The digital memory device further includes a second conducting area on the surface of a substrate. At the first stable position of the moveable element, a first gap exists between the first conducting area and the second conducting area. At the second stable position of the moveable element, a second gap that is smaller than the first gap exists between the first conducting area and the second conducting area. In at least the second stable position, an attractive Casimir force between the moveable element and the substrate holds the moveable element in the stable position.

A digital memory device includes a moveable element that is configured to move between a first stable position and a second stable position, where the moveable element comprises a first conducting area. The digital memory device further includes a second conducting area on the surface of a substrate. At the first stable position of the moveable element, a first gap exists between the first conducting area and the second conducting area. At the second stable position of the moveable element, a second gap that is smaller than the first gap exists between the first conducting area and the second conducting area. In at least the second stable position, an attractive Casimir force between the moveable element and the substrate holds the moveable element in the stable position.

A method for page writes for triple or higher level cell flash memory is provided. The method includes receiving data in a storage system, from a client that is agnostic of page write requirements for triple or higher level cell flash memory, wherein the page write requirements specify an amount of data and a sequence of writing data for a set of pages to assure read data coherency for the set of pages. The method includes accumulating the received data, in random-access memory (RAM) in the storage system to satisfy the page write requirements for the triple or higher level cell flash memory in the storage system. The method includes writing at least a portion of the accumulated data in accordance with the page write requirements, from the RAM to the triple level cell, or the higher level cell, flash memory in the storage system as an atomic write.

A neural network method and device are included, A neural network circuit includes a synaptic memory cell including a resistive memory element, which is disposed along an output line and which can have a first resistance value and a second resistance value as a resistance value, the synaptic memory cell generates a column signal, based on the resistance value of the resistive memory element and an input signal received via an input line, a reference memory cell including a reference memory element, which is disposed along a reference line and which has a resistance value that is a ratio of the first and second resistance values, the reference memory cell generates a reference signal, based on the resistance value of the reference memory element and the input signal, and an output circuit generates an output signal for the output line based on the column signal and the reference signal.

Methods for input/output voltage training of a three-dimensional (3D) memory device is disclosed. The method can comprise the following operations: (1) setting a reference voltage value at an on-die termination (ODT) enabled status; (2) controlling the 3D memory device to perform a write training process; (3) determining whether a further write training process is needed; (4) in response to determining that the further write training process is needed, repeating operations (1), (2) and (3); and (5) in response to determining that the further write training process is not needed, setting the reference voltage value as an optimized reference voltage value.

A semiconductor device includes a substrate having an active cell region and an interfacial region adjacent to each other in a first direction, bit lines on the active cell region of the substrate that are spaced apart from each other in a second direction that intersects the first direction, and bit-line pads on the interfacial region of the substrate that are spaced apart from each other in the second direction. Each of the bit lines includes a first bit line and a second bit line that extend in the first direction and are spaced apart from each other in the second direction, a connection part that connects a first end of the first bit line to a second end of the second bit line, and a coupling part that connects one of the bit-line pads to one of the first bit line, the second bit line, and the connection part.