Technologies relating to analog-to-analog quantizers with an intrinsic Rectified Linear Unit (ReLU) function designed for in-memory computing are disclosed. An apparatus, in some implementations, includes: a DAC; a first crossbar connected to the DAC; a first analog quantizer connected to the first crossbar; a buffer connected to the first analog quantizer; a second crossbar connected to the buffer; and an ADC connected to the second crossbar.

The present disclosure provides a memory device, which includes a plurality of electrically bipolar variable memory devices and a storage transistor. The electrically bipolar variable memory devices are electrically connected to a plurality of word lines respectively, the storage transistor is electrically connected to the electrically bipolar variable memory devices, where one end of each of the electrically bipolar variable memory devices is electrically connected to a corresponding one of the word lines, and another end of each of the electrically bipolar variable memory devices is electrically connected to the gate of the storage transistor.

An electronic device comprises a semiconductor memory that includes: a memory cell; a protective layer disposed along a profile of the memory cell; and a buffer layer interposed between at least a portion of a sidewall of the memory cell and the protective layer, wherein the buffer layer and the protective layer include silicon nitride, and wherein a density of the protective layer is greater than a density of the buffer layer.

Carbon nanotube (CNT) memory cell elements and methods of forming CNT memory cell elements are provided. A CNT memory cell may comprise a CNT memory cell element, e.g., in combination with a transistor. A CNT memory cell element may include a metal/CNT layer/metal (M/CNT/M) structure formed between adjacent metal interconnect layers or between a silicided active layer (e.g., including MOSFET devices) and a metal interconnect layer. The M/CNT/M structure may be formed by a process including forming a tub opening in a dielectric region, forming a cup-shaped bottom electrode in the tub opening, forming a cup-shaped CNT layer in an interior opening defined by the cup-shaped bottom electrode, and forming a top electrode in an interior opening defined by the cup-shaped CNT layer.

A switching device including a GaN substrate; an unintentionally doped GaN layer on a first surface of the GaN substrate; a regrown unintentionally doped GaN layer on the unintentionally doped GaN layer; a regrowth interface between the unintentionally doped GaN layer and the regrown unintentionally doped GaN layer; a p-GaN layer on the regrown unintentionally doped GaN layer; a first electrode on the p-GaN layer; and a second electrode on a second surface of the GaN substrate.

A method for manufacturing a nonvolatile semiconductor storage device includes: forming a first conductive layer by self-alignment on a first wiring layer, and performing an annealing processing; stacking a first stacked film on the first conductive layer; processing the first stacked film, the first conductive layer, and the first wiring layer into a stripe structure extending in a first direction; forming and planarizing a first interlayer insulating film; forming a second wiring layer; forming a second conductive layer by self-alignment on the second wiring layer, and performing an annealing processing; processing the second wiring layer and the second conductive layer into a stripe structure extending in a second direction intersecting the first direction; and processing the first stacked film and the first interlayer insulating film below and between the second wiring layer, and forming a first memory cell having the first stacked film in a columnar shape.

A pseudo-analog memory computing circuit includes at least one input circuit, at least one output circuit and at least one pseudo-analog memory computing unit. Each pseudo-analog memory computing unit is coupled between one of the at least one input circuit and one of the at least one output circuit and has at least one weight mode. Each pseudo-analog memory computing unit generates at least first computing result for a coupled output circuit according to a weight of a selected weight mode and at least one input signals of a coupled input circuit.

A system includes a processor, and a resistive processing resistive processing unit coupled to the processor. The resistive processing unit includes an array of cells, wherein the cells respectively include resistive devices, wherein at least a portion of the resistive devices are programmable to store weight values of a given matrix in the array of cells. When the given matrix is stored in the array of cells, the processor is configured to perform a weight extraction process. The weight extraction process applies a set of input vectors to the resistive processing unit to perform analog matrix-vector multiplication operations on the stored matrix, obtains a set of output vectors resulting from the analog matrix-vector multiplication operations, and determines weight values of the given matrix stored in the array of cells utilizing the set of input vectors and the set of output vectors.

A semiconductor storage device includes a memory cell including a core portion that extends in a first direction above a semiconductor substrate; a variable resistance layer that extends in the first direction and is in contact with the core portion; a semiconductor layer that extends in the first direction and is in contact with the variable resistance layer; a first insulator layer that extends in the first direction and is in contact with the semiconductor layer; and a first voltage applying electrode that extends in a second direction orthogonal to the first direction and is in contact with the first insulator layer. The core portion is a vacuum region, or a region containing inert gas.

An analog neuromorphic circuit is disclosed, having input voltages applied to a plurality of inputs of the analog neuromorphic circuit. The circuit also includes a plurality of resistive memories that provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel. The circuit also includes at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. The multiplying of each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.