An example apparatus can include a memory array and a memory controller. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second plurality of memory cells. The memory controller can be coupled to the first portion and the second portion. The memory controller can be configured to operate the first plurality of memory cells for short-term memory operations. The memory controller can be further configured to operate the second plurality of memory cells for long-term memory operations.

Provided is a 3D synapse device stack, a 3D stackable synapse array using the same, and a method for manufacturing the 3D synapse device stack. The 3D synapse device stack comprises: a channel hole provided along a vertical direction on a substrate; a semiconductor body formed by applying a semiconductor material to the surface of the channel hole; first insulating layers and sources alternately stacked on a first side surface of an outer circumferential surface of the semiconductor body; first insulating layers and drains alternately stacked on a second side surface of an outer circumferential surface of the semiconductor body; a source line electrode connected to and in contact with a plurality of sources; a drain line electrode connected to and in contact with the plurality of drains; a plurality of word lines alternately stacked with first insulating layers on a third side surface of an outer circumferential surface of the semiconductor body; and a plurality of insulator stacks positioned between the word lines and the semiconductor body, wherein the semiconductor body, the source, the drain, the insulator stack, and the word line positioned on the same layer on the surface of the channel hole constitute a synapse device or a part thereof. The synapse device stack may implement an AND-type or NOR-type synapse array.

A method is presented for mapping weights for kernels of a neural network onto a crossbar array. In one example, the crossbar array is comprised of an array of non-volatile memory cells arranged in columns and rows, such that memory cells in each row of the array is interconnected by a respective drive line and each column of the array is interconnected by a respective bit line; and wherein each memory cell is configured to receive an input signal indicative of a multiplier and operates to output a product of the multiplier and a weight of the given memory cell onto the corresponding bit line of the given memory cell, where the value of the multiplier is encoded in the input signal and the weight of the given memory cell is stored by the given memory cell.

A ferroelectric tunnel junction (FTJ) memory device may include a first electrode and a ferroelectric layer comprising ferroelectric dipoles that may generate a first electric field. The first electric field may be oriented in a first direction when the device operates in an ON state. The device may also include a barrier layer that may generate a depolarizing second electric field that may be oriented in a second direction opposite of the first direction when the device operates in the ON state. The device may further include a second electrode. The first electrode and the second electrode may generate a third electric field that is oriented in the first direction when the device operates in the ON state.

Disclosed herein are related to a memory system and a method of operating the memory system. In one aspect, resistances of a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell are individually set. In one aspect, the first memory cell and the second memory cell are coupled to each other in series between a first line and a second line, and the third memory cell and the fourth memory cell are coupled to each other in series between the second line and a third line. In one aspect, current through the second line according to a parallel resistance of i) a first series resistance of the first memory cell and the second memory cell, and ii) a second series resistance of the third memory cell and the fourth memory cell is sensed. According to the sensed current, multi-level data can be read.

A variable resistive memory device includes a memory cell, a first current-applying block, a second current-applying block and a mode setting circuit. The memory cell includes a first electrode, a second electrode, and a memory layer, the memory layer interposed between the first electrode and the second electrode. The first current-applying block is configured to flow a first current to the first electrode that flows from the first electrode to the second electrode. The second current-applying block is configured to flow a second current to the second electrode that flows from the second electrode to the first electrode. The mode setting circuit is configured to selectively provide any one of the first electrode of the first current-applying block and the second electrode of the second current-applying block with a first voltage. When the memory cell is selected, the selected current-applying block, among the first current-applying block and the second current-applying block, is driven. When the first current-applying block is selected, a second voltage is applied to the second electrode. When the second current-applying block is selected, the second voltage is applied to the first electrode. The first voltage has a voltage level by a threshold voltage higher than the second voltage.

According to an embodiment, a reinforcement learning system includes a memristor array in which each of a plurality of first direction lines corresponds to one of a plurality of states, and each of a plurality of second direction lines corresponds to one of a plurality of actions, a first voltage application unit that individually applies voltage to the first direction lines, a second voltage application unit that individually applies voltage to the second direction lines, a action decision circuit that decides action to be selected by an agent in a state corresponding to a first direction line to which a readout voltage is applied, a action storage unit that stores action selected by the agent in each state that can be caused in an environment, and a trace storage unit that stores a time at which the state is caused by action selected by the agent.

Various embodiments of the present disclosure are directed towards a memory device including a first memory element and a second memory element. The memory device includes a substrate and a bottom electrode disposed over the substrate. The first memory element is disposed between the bottom electrode and a top electrode, such that the first memory element has a first area. A second memory element is disposed between the bottom electrode and the top electrode. The second memory element is laterally separated from the first memory element by a non-zero distance. The second memory element has a second area different than the first area.

A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.

A memory-centric neural network system and operating method thereof includes: a processing unit; semiconductor memory devices coupled to the processing unit, the semiconductor memory devices containing instructions executed by the processing unit; a weight matrix constructed with rows and columns of memory cells, inputs of the memory cells of a same row being connected to one of axons, outputs of the memory cells of a same column being connected to one of neurons; timestamp registers registering timestamps of the axons and the neurons; and a lookup table containing adjusting values indexed in accordance with the timestamps, wherein the processing unit updates the weight matrix in accordance with the adjusting values.