Power consumption of a semiconductor device is reduced efficiently. The semiconductor device includes a power management unit, a cell array, and a peripheral circuit for driving the cell array. The cell array includes a word line, a bit line pair, a memory cell, and a backup circuit for backing up data in the memory cell. A row circuit and a column circuit are provided in a first power domain capable of power gating, and the cell array is provided in a second power domain capable of power gating. In the operation mode of a memory device, a plurality of low power consumption modes, which have lower power consumption than the standby mode, are set. The power management unit selects one from the plurality of low power consumption modes and performs control for bringing the memory device into the selected low power consumption mode.

Disclosed is a semiconductor memory device including a memory cell based on a static random access memory having a 6T or 4T2R configuration and including a first internal node, a second internal node, a first ferroelectric capacitor, and a second ferroelectric capacitor, the first ferroelectric capacitor and the second ferroelectric capacitor having respective first ends connected respectively to the first internal node and the second internal node. For recovering data stored in a non-volatile fashion in the first ferroelectric capacitor and the second ferroelectric capacitor, a first access transistor connected between the first internal node and a first bit line and a second access transistor connected between the second internal node and a second bit line are turned on, and respective capacitive components of the first bit line and the second bit line are used as load capacitances.

A semiconductor device includes a latch including a first-node and a second-node. A first-transistor is between the first-node and a first-BL and has a gate connected to a WL. A second-transistor is between the second-node and a second-BL and has a gate connected to the WL. A power-supply line is connected to the latch. A third-transistor is connected between the first-node and a reference-voltage source. A fourth-transistor is between the second-node and the reference-voltage source and has a gate connected to the reference-voltage source. A signal line is connected to a gate of the third-transistor. In a first-mode, the power-supply line supplies a first-voltage to the latch and the signal line brings the third-transistor to a non-conduction state. In a second-mode, the power-supply line supplies a second-voltage to the latch and the signal line brings the third-transistor to a conduction state and connects the first-node to the reference-voltage source.

A semiconductor integrated circuit according to an embodiment includes: first to third wiring lines; first memory elements disposed in a cross region between the first wiring lines and the second wiring lines; second memory elements disposed in a cross region between the first wiring lines and the third wiring lines; a first write control circuit connected to the first wiring lines: a first circuit connected to one of the second wiring lines and supplying a first potential; a second circuit connected to the other one of the second wiring lines and supplying a second potential lower than the first potential; SRAM cells connected to the third wiring lines; and a selection circuit including input terminals electrically connected to the first wiring lines and an output terminal, the selection circuit connecting one of the input terminals to the output terminal in accordance with an input signal.

The present invention provides a memory device, the memory device includes a first region having a plurality of oxide semiconductor static random access memories (OSSRAM) arranged in a first direction, and each of the OSSRAMs comprising a static random access memory (SRAM) and at least an oxide semiconductor dynamic random access memory (DOSRAM), wherein the DOSRAM is connected to the SRAM, wherein each of the DOSRAMs comprises an oxide semiconductor gate (OSG), and each of the OSGs extending in a second direction perpendicular to the first direction, and an oxide semiconductor channel extending in the first direction, an oxide semiconductor gate connection extending in the first direction to connect each of the OSGs, and a word line, a Vcc connection line and a Vss connection line extend in the first direction and are connected to the SRAMs in each OSSRAM.

To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion configured to hold data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, a capacitor electrically connected to a source electrode or a drain electrode of the transistor is included.

A configuration memory cell includes a latch portion including a cross-coupled latch having complementary output nodes, and a programmable read-only memory (PROM) portion coupled to one of the complementary output nodes of the latch portion, the PROM portion including a programmable and erasable ReRAM device.

A static random-access memory (SRAM) cell includes a non-inverting logic element having an input and an output. A vertical resistor feedback device is connected between the output and the input of the non-inverting logic element.

A configuration memory circuit according to an embodiment includes: a first and second wirings; and a first to eighth transistors, the first and fourth transistors having a first-conductive-type, the second, third, fifth, and sixth transistors having a second-conductive-type, the first to third transistors being connected in series, the fourth to sixth transistors being connected in series, gates of the first and third transistors being connected to the first wiring, one of a source and a drain of the seventh transistor, and the first wiring, a gate of the second transistor being connected to a third wiring, gates of the fourth and sixth transistors being connected to the second wiring, one of a source and a drain of the eighth transistor, and the second wiring, a gate of the fifth transistor being connected to the third wiring, gates of the seventh and eighth transistors being connected to a fifth wiring.

The present invention provides a memory device, the memory device includes a first region having a plurality of oxide semiconductor static random access memories (OSSRAM) arranged in a first direction, and each of the OSSRAMs comprising a static random access memory (SRAM) and at least an oxide semiconductor dynamic random access memory (DOSRAM), wherein the DOSRAM is connected to the SRAM, wherein each of the DOSRAMs comprises an oxide semiconductor gate (OSG), and each of the OSGs extending in a second direction perpendicular to the first direction, and an oxide semiconductor channel extending in the first direction, an oxide semiconductor gate connection extending in the first direction to connect each of the OSGs, and a word line, a Vcc connection line and a Vss connection line extend in the first direction and are connected to the SRAMs in each OSSRAM.