A non-volatile programmable circuit configurable to perform logic functions, is provided. The programmable circuit can employ two-terminal non-volatile memory devices to store information, thereby mitigating or avoiding disturbance of programmed data in the absence of external power. Two-terminal resistive switching memory devices having high current on/off ratios and fast switching times can also be employed for high performance, and facilitating a high density array. For look-up table applications, input/output response times can be several nanoseconds or less, facilitating much faster response times than a memory array access for retrieving stored data.

A memory cell comprises an elevationally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two programmable states characterized by two different V.sub.t's of the programmable transistor. The programmable transistor comprises a top source/drain region and a bottom source/drain region. A bottom select device is electrically coupled in series with and elevationally inward of the bottom source/drain region of the programmable transistor. A top select device is electrically coupled in series with and is elevationally outward of the top source/drain region of the programmable transistor. A bottom select line is electrically coupled in series with and is elevationally inward of the bottom select device. A top select line is electrically coupled in series with and is elevationally outward of the top select device. Other embodiments are disclosed.

A non-volatile associative memory cell includes: one magnetoresistance effect element including first and second ferromagnetic layers and a non-magnetic layer; first and second match lines connected to the magnetoresistance effect element in accordance with predetermined first and second search line voltages. The magnetoresistance effect element includes: first and second members. The first member includes first and second electrodes disposed at opposite ends. The first ferromagnetic layer is in the first or second member, the non-magnetic layer is stacked in the first direction, and the direction of internal magnetization of the first ferromagnetic layer changes in a case in which a current flows between the first and second electrodes. The non-magnetic and the second ferromagnetic layers are in the second member. A magnetoresistance effect element resistance value changes. An electric potential corresponding to an second ferromagnetic layer electric potential is applied to each of the first and second match lines.

The disclosure relates in some aspects to on-chip processing circuitry formed within the die of a non-volatile (NVM) array to perform data searches. In some aspects, the die includes components configured to sense wordlines of stored data in the NVM array by applying voltages on the wordlines serially, and then search for an input data pattern within the serially-sensed wordlines. In some examples, the components of the die include latches and circuits configured to perform bitwise latch logic search operations. In other examples, the search components are configured with under-the-array or next-to-the-array dedicated search circuitry that uses registers and/or random access memory (RAM). Other aspects relate to a separate controller device for controlling the on-chip NVM search operations. For example, the controller may determine whether to search for data using search components of the NVM die or processors of the controller based, e.g., on a degree of fragmentation of data.

A method of detecting error in a data plane of a packet forwarding element that includes a plurality of physical ternary content-addressable memories (TCAMs) is provided. The method configures a first set of physical TCAMs into a first logical TCAM. The method configures a second set of physical TCAMs into a second logical TCAM. The second logical TCAM includes the same number of physical TCAMs as the first logical TCAM. The method programs the first and second logical TCAMs to store a same set of data. The method requests a search for a particular content from the first and second logical TCAMs. The method generates an error signal when the first and second logical TCAMs do not produce a same search results.

A semiconductor structure is provided. The semiconductor structure includes: a substrate; a magnetic layer over the substrate; a magnetic tunnel junction (MTJ) cell over the magnetic layer; and a non-magnetic conductive layer between the magnetic layer and the MTJ cell. An associated method for fabricating the semiconductor structure is also disclosed.

In order to provide a technique for reducing an area of a content addressable memory cell and suppressing a leak current in a content addressable memory which calculates similarity, a content addressable memory cell of the present invention, comprising: a resistance network which includes plural current paths, a logic circuit for selecting a current path in response to input data, and a variable-resistance-type non-volatile memory element that is arranged on at least one current path and stores data and whose resistance value is changed according to a result of logical calculation based on the input data and the stored data; and a charge/discharge circuit which is connected with the resistance network and a match line and whose delay time from inputting a signal through the match line until outputting the signal is changed according to the result of logical calculation based on the input data and the stored data.

In order to provide a technique for reducing an area of a content addressable memory cell and suppressing a leak current in a content addressable memory which calculates similarity, a content addressable memory cell of the present invention, comprising: a resistance network which includes plural current paths, a logic circuit for selecting a current path in response to input data, and a variable-resistance-type non-volatile memory element that is arranged on at least one current path and stores data and whose resistance value is changed according to a result of logical calculation based on the input data and the stored data; and a charge/discharge circuit which is connected with the resistance network and a match line and whose delay time from inputting a signal through the match line until outputting the signal is changed according to the result of logical calculation based on the input data and the stored data.

A hardware forwarding element is provided that includes a group of unit memories, a set of packet processing pipelines, and an error signal fabric. Each packet processing pipeline includes several of match action stages. Each match action stage includes a set of match action tables stored in a set of unit memories. Each unit memory is configured to detect an error in the unit memory and generate an error output when an error is detected in the memory unit. The error signal fabric, for each match action stage, combines error outputs of the unit memories storing match tables into a first bit in the error signal fabric. The error signal fabric, for each match action stage, combines error outputs of the unit memories storing action tables into a second bit in the error signal fabric.

Data bit inversion tracking in cache memory to reduce data bits written for write operations is disclosed. In one aspect, a cache memory including a cache controller and a cache array is provided. The cache array includes one or more cache entries, each of which includes a cache data field and a bit change track field. The cache controller compares a current cache data word to a new data word to be written and stores a bit track change word representing the difference (i.e., inverted bits) between the current cache data word and the new data word in the bit change track field. By using the bit track change word stored in the bit change track field to determine whether fewer bit writes are required to write data in an inverted or a non-inverted form, power consumption can be reduced for write operations through reduced bit write operations.