A semiconductor device, the device including: a first silicon layer including first single crystal silicon; an isolation layer disposed over the first silicon layer; a first metal layer disposed over the isolation layer; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the isolation layer includes an oxide to oxide bond surface, where the plurality of transistors include a second single crystal silicon region; and a third metal layer disposed over the first level, where a typical first thickness of the third metal layer is at least 50% greater than a typical second thickness of the second metal layer.

A semiconductor device, the device including: a first silicon layer including first single crystal silicon; an isolation layer disposed over the first silicon layer; a first metal layer disposed over the isolation layer; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the isolation layer includes an oxide to oxide bond surface, where the plurality of transistors include a second single crystal silicon region; and a third metal layer disposed over the first level, where a typical first thickness of the third metal layer is at least 50% greater than a typical second thickness of the second metal layer.

A 3D semiconductor device including: a first level including a first single crystal layer, the first level including a plurality of first transistors and at least one first metal layer, where the at least one first metal layer overlays the first single crystal layer, and where the at least one first metal layer includes interconnects between the first transistors forming first control circuits; a second metal layer overlaying the at least one first metal layer; a second level overlaying the second metal layer, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors, where the second level includes a plurality of first memory cells, the first memory cells each including at least one of the second transistors, where the third level includes second memory cells, the second memory cells each including third transistors.

A 3D semiconductor device including: a first level including a first single crystal layer, the first level including a plurality of first transistors and at least one first metal layer, where the at least one first metal layer overlays the first single crystal layer, and where the at least one first metal layer includes interconnects between the first transistors forming first control circuits; a second metal layer overlaying the at least one first metal layer; a second level overlaying the second metal layer, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors, where the second level includes a plurality of first memory cells, the first memory cells each including at least one of the second transistors, where the third level includes second memory cells, the second memory cells each including third transistors.

An unbalanced plane management method, an associated data storage device and the controller thereof are provided. The unbalanced plane management method may include: setting an unbalanced plane number; selecting at least one plane with a plane count calculated by subtracting the unbalanced plane number from a maximum plane number, and recording at least one set of blocks of the at least one plane to a block skip table; according to block numbers as indexes, combining blocks of unselected planes into superblocks, wherein said superblocks respectively correspond to said block numbers; and recording total capacity of all superblocks and the unbalanced plane number, to generate a latest record of records of multiple types of storage capacity, for further setting storage capacity configuration of the data storage device, wherein said all superblocks include said superblocks.

A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, and at least one first metal layer-which includes interconnects between the first transistors forming control circuits-which overlays the first single crystal layer; a second metal layer overlaying first metal layer; a second level including second transistors, first memory cells (each including at least one second transistor) and overlaying second metal layer; a third level including third transistors (at least one includes a polysilicon channel), second memory cells (each including at least one third transistor and cell is partially disposed atop control circuits) and overlaying the second level; control circuits control data written to second memory cells; third metal layer disposed above third level; fourth metal layer includes a global power distribution grid, has a thickness at least twice the second metal layer, and is disposed above third metal layer.

A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, and at least one first metal layer-which includes interconnects between the first transistors forming control circuits-which overlays the first single crystal layer; a second metal layer overlaying first metal layer; a second level including second transistors, first memory cells (each including at least one second transistor) and overlaying second metal layer; a third level including third transistors (at least one includes a polysilicon channel), second memory cells (each including at least one third transistor and cell is partially disposed atop control circuits) and overlaying the second level; control circuits control data written to second memory cells; third metal layer disposed above third level; fourth metal layer includes a global power distribution grid, has a thickness at least twice the second metal layer, and is disposed above third metal layer.

The present application discloses a serial flash memory, including a memory array, a row decoder, a column decoder, a control module, and an SPI interface, wherein the control module includes a row enable signal; and when the last bit of an SPI row address in an SPI address signal is to be read, the control module enables the row enable signal, and the row enable signal enables an internal row address of an internal address of the serial flash memory to be valid and enables the row decoder to perform decoding and select the internal row address. The present application further provides an address control method of a serial flash memory. In the present application, the timing requirement on the row address can be relaxed, the area of the row decoder can be reduced, and the area of the row drive circuit can be reduced.

The present application discloses a serial flash memory, including a memory array, a row decoder, a column decoder, a control module, and an SPI interface, wherein the control module includes a row enable signal; and when the last bit of an SPI row address in an SPI address signal is to be read, the control module enables the row enable signal, and the row enable signal enables an internal row address of an internal address of the serial flash memory to be valid and enables the row decoder to perform decoding and select the internal row address. The present application further provides an address control method of a serial flash memory. In the present application, the timing requirement on the row address can be relaxed, the area of the row decoder can be reduced, and the area of the row drive circuit can be reduced.

An unbalanced plane management method, an associated data storage device and the controller thereof are provided. The unbalanced plane management method may include: setting an unbalanced plane number; selecting at least one plane with a plane count calculated by subtracting the unbalanced plane number from a maximum plane number, and recording at least one set of blocks of the at least one plane to a block skip table; according to block numbers as indexes, combining blocks of unselected planes into superblocks, wherein said superblocks respectively correspond to said block numbers; and recording total capacity of all superblocks and the unbalanced plane number, to generate a latest record of records of multiple types of storage capacity, for further setting storage capacity configuration of the data storage device, wherein said all superblocks include said superblocks.