A semiconductor device includes a logic circuit, a memory, and a storage device. The storage device has a first special information storage region into which special information is written before a solder reflow process, a second special information storage region into which special information for updating is written after the solder reflow process, and a data storage region. The first special information storage region is constituted by a memory cell having a high reflow resistance and in which data is retained even after the solder reflow process. The second special information storage region and the data storage region are constituted by memory cells having a low reflow resistance and in which data may not be retained during the solder reflow process.

A semiconductor device includes a memory cell array, which further includes an array of first magnetic memory cells and an array of second magnetic memory cells. Each of the first magnetic memory cells includes a first magnetic tunnel junction structure having a reversible resistance state, and each of the second magnetic memory cells includes a second magnetic tunnel junction structure having a one-time programmable (OTP) resistance state.

A semiconductor device includes a memory cell array, which further includes an array of first magnetic memory cells and an array of second magnetic memory cells. Each of the first magnetic memory cells includes a first magnetic tunnel junction structure having a reversible resistance state, and each of the second magnetic memory cells includes a second magnetic tunnel junction structure having a one-time programmable (OTP) resistance state.

A semiconductor device includes a memory cell array, which further includes an array of first magnetic memory cells and an array of second magnetic memory cells. Each of the first magnetic memory cells includes a first magnetic tunnel junction structure having a reversible resistance state, and each of the second magnetic memory cells includes a second magnetic tunnel junction structure having a one-time programmable (OTP) resistance state.

A semiconductor device includes a memory cell array, which further includes an array of first magnetic memory cells and an array of second magnetic memory cells. Each of the first magnetic memory cells includes a first magnetic tunnel junction structure having a reversible resistance state, and each of the second magnetic memory cells includes a second magnetic tunnel junction structure having a one-time programmable (OTP) resistance state.

An integrated circuit may include an AI logic circuit, and an embedded one-time programmable (OTP) MRAM memory electrically coupled to the AI logic circuit. The embedded OTP MRAM memory may include multiple storage cells, one or more reference resistors, and a memory-reading circuit for determining the state of each storage cell. The reading circuit may include: a multiplexer configured to electrically couple each storage cell to a reference resistor; a source line selectively providing an input electrical signal to each storage cell to generate a first output signal; a driving circuit providing an input electrical signal to the reference resistor to generate a second output signal; and a comparator configured to compare the first output signal and the second output signal to generate an output signal that indicates the state of each storage cell. Each reference resistor may be shared among multiple storages in an array or multiple storage arrays.

An integrated circuit may include an AI logic circuit, and an embedded one-time programmable (OTP) MRAM memory electrically coupled to the AI logic circuit. The embedded OTP MRAM memory may include multiple storage cells, one or more reference resistors, and a memory-reading circuit for determining the state of each storage cell. The reading circuit may include: a multiplexer configured to electrically couple each storage cell to a reference resistor; a source line selectively providing an input electrical signal to each storage cell to generate a first output signal; a driving circuit providing an input electrical signal to the reference resistor to generate a second output signal; and a comparator configured to compare the first output signal and the second output signal to generate an output signal that indicates the state of each storage cell. Each reference resistor may be shared among multiple storages in an array or multiple storage arrays.

A semiconductor device includes a memory cell array, which further includes an array of first magnetic memory cells and an array of second magnetic memory cells. Each of the first magnetic memory cells includes a first magnetic tunnel junction structure having a reversible resistance state, and each of the second magnetic memory cells includes a second magnetic tunnel junction structure having a one-time programmable (OTP) resistance state.

A semiconductor device includes a memory cell array, which further includes an array of first magnetic memory cells and an array of second magnetic memory cells. Each of the first magnetic memory cells includes a first magnetic tunnel junction structure having a reversible resistance state, and each of the second magnetic memory cells includes a second magnetic tunnel junction structure having a one-time programmable (OTP) resistance state.

One-time programming (OTP) magneto-resistive random access memory (MRAM) bit cells in a physically unclonable function (PUF) memory in breakdown to a memory state from a previous read operation to provide PUF operations is disclosed. PUF memory is configured to permanently one-time program an initial randomly generated PUF output from PUF MRAM bit cells accessed in an initial PUF read operation, to the same PUF MRAM bit cells accessed in the initial PUF read operation. In this manner, the initial PUF output is randomly generated due to process variations of the PUF MRAM bit cells to maintain an initial unpredictable memory state, but the PUF output will be reproduced for subsequent PUF read operations to the same PUF MRAM bit cells in the PUF memory array for reproducibility. The OTP of the PUF MRAM bit cells can be accomplished by applying breakdown voltage to the PUF MRAM bit cells during programming.