A method for applying and propagating superconducting signals in a superconducting memory circuit is provided. The memory circuit includes passive cells and at least one power-signal propagation circuit. The method includes: configuring the memory circuit such that the passive cells are arranged into sets, each set of passive cells having associated therewith at least one common superconducting wire interconnecting a subset of the passive cells; configuring the memory circuit such that an input of the power-signal propagation circuit is coupled to a preceding set of passive cells via a first superconducting wire, and an output of the power-signal propagation circuit is coupled to a subsequent set of passive cells via a second superconducting wire; applying a first superconducting signal to the first superconducting wire; and applying a second superconducting signal to the second superconducting wire in response to applying the first superconducting signal to the first superconducting wire.

The present disclosure is drawn to, among other things, an antifuse circuit. The antifuse circuit includes a plurality of antifuse bitcells and a reference resistor. Each antifuse bitcell includes two or more memory bits and a reference resistor. The two or more memory bits are configured to be in a programmed state and at least one unprogrammed state.

A one-time programmable (OTP) latch includes a memory cell having a first non-volatile (NV) resistive element and a second NV resistive element, cross-coupled inverter circuitry, a first transistor having a first current electrode coupled to a first node of the cross-coupled inverter circuitry and a second current electrode coupled to a first terminal of the first NV resistive element, and a second transistor having a first current electrode coupled to a second node of the cross-coupled inverter circuitry, different from the first node, and a second current electrode coupled to a first terminal of the second NV resistive element. The OTP latch also includes write circuitry coupled to the memory cell and configured to program only one of the first NV resistive element or the second NV resistive element to an OTP state while the cross-coupled inverter circuitry is isolated from the memory cell by the first and second transistors.

According to an embodiment, a magnetic storage device includes a first, second, and third magnetoresistive effect elements, and a controller. The second and third magnetoresistive effect elements are in proximity to the first magnetoresistive effect element. When the controller receives an command which is associated with an operation of writing a first data item to the first magnetoresistive effect element, the controller is configured to perform a first operation of writing the first data item to the first magnetoresistive effect element, and a second operation of writing a second data item different from the first data item to the second magnetoresistive effect element and the third magnetoresistive effect element.

A magnetic memory device is provided. The magnetic memory device includes a memory circuit comprising a first tunnel magnetoresistive element and a second tunnel magnetoresistive element coupled in series. An input node of the magnetic memory device is coupled to the first tunnel magnetoresistive element, wherein the input node is configured to receive a voltage signal. The first tunnel magnetoresistive element initially holds a first resistance value, wherein the first tunnel magnetoresistive element is short-circuited to hold a second resistance value after the voltage signal is received by the input node. End nodes of the memory circuit are coupled to defined voltages in a read mode. The magnetic memory device further includes a read-out circuit configured to measure a voltage at a sensing node in the read mode. The sensing node is interconnected between the first tunnel magnetoresistive element and the second tunnel magnetoresistive element.

In a particular aspect, an apparatus includes a magnetic random access memory (MRAM) cell including a pair of cross coupled inverters including a first inverter and a second inverter. The first inverter includes a first transistor coupled to a first node and a second transistor coupled to the first node. The second inverter includes a third transistor coupled to a second node and a fourth transistor coupled to the second node. The MRAM cell includes a first magnetic tunnel junction (MTJ) element coupled to the second transistor and a second MTJ element coupled to the fourth transistor. The apparatus further includes a voltage initialization circuit coupled to the MRAM cell. The voltage initialization circuit is configured to substantially equalize voltages of the first node and the second node in response to an initialization signal.

A memory device includes a plurality of magnetoresistive random-access memory (MRAM) cells including a first one-time programmable (OTP) MRAM cell. A first OTP select transistor is connected to the first OTP MRAM cell. The first OTP select transistor configured to selectively apply a breakdown current to the first OTP MRAM cell to write the first OTP MRAM cell to a breakdown state.

A circuit and method for adaptive trimming of the reference signal for sensing data during a read operation of magnetic memory cells to improve read margin for the magnetic memory cells. The circuit has a trim one-time programmable memory array programmed with offset trim data applied to magnetic memory array sense amplifiers. Sense amplifier trimming circuits receive and decode the trim data to determine offset trim signal magnitude to adjust the reference signal to improve the read margin. The method sets the offset trim level to each increment of the offset trim level. Data is written and read to the magnetic memory array, the number of errors in the array is accumulated for each setting of the offset trim level. The error levels are compared and the appropriate trim level is programmed to the trim memory cells such that a read margin of the sense amplifier is improved.

A circuit and method for adaptive trimming of the reference signal for sensing data during a read operation of magnetic memory cells to improve read margin for the magnetic memory cells. The circuit has a trim one-time programmable memory array programmed with offset trim data applied to magnetic memory array sense amplifiers. Sense amplifier trimming circuits receive and decode the trim data to determine offset trim signal magnitude to adjust the reference signal to improve the read margin. The method sets the offset trim level to each increment of the offset trim level. Data is written and read to the magnetic memory array, the number of errors in the array is accumulated for each setting of the offset trim level. The error levels are compared and the appropriate trim level is programmed to the trim memory cells such that a read margin of the sense amplifier is improved.

A memory device having features of the present invention comprises a reprogrammable memory portion including therein a first plurality of magnetic tunnel junctions (MTJs) whose resistance is switchable; and a one-time-programmable (OTP) memory portion including therein a second plurality of MTJs whose resistance is switchable and a third plurality of MTJs whose resistance is fixed. Each MTJ of the first, second, and third plurality of MTJs includes a magnetic free layer having a magnetization direction substantially perpendicular to a layer plane thereof and a magnetic reference layer having a fixed magnetization direction substantially perpendicular to a layer plane thereof. The second plurality of MTJs represents one of two logical states and the third plurality of MTJs represents the other one of the two logical states.