A write driver writes one of binary data into an OTP memory cell using a boost voltage or a regulator voltage. An OTP voltage select register causes the write driver to select one of two voltages. The trimming registers hold voltage setting values defining magnitudes of two voltages, respectively. An OTP voltage trimming step is a step of sequentially changing the voltage setting values in a high voltage direction while writing is performed into a plurality of OTP memory cells one by one using one of the two voltage setting values as a trimming target, until writing with the same voltage setting value succeeds in succession writing with the same voltage setting value is successively successful in N OTP memory cells.

A write driver writes one of binary data into an OTP memory cell using a boost voltage or a regulator voltage. An OTP voltage select register causes the write driver to select one of two voltages. The trimming registers hold voltage setting values defining magnitudes of two voltages, respectively. An OTP voltage trimming step is a step of sequentially changing the voltage setting values in a high voltage direction while writing is performed into a plurality of OTP memory cells one by one using one of the two voltage setting values as a trimming target, until writing with the same voltage setting value succeeds in succession writing with the same voltage setting value is successively successful in N OTP memory cells.

Provided is a memory device configured to control such that a first electrical signal is applied to the normal memory cell during a read operation of the normal memory cell and a second electrical signal having a magnitude greater than that of the first electrical signal is applied to the OTP memory cell during a read operation of the OTP memory cell, a read driver configured to provide the first electrical signal to the normal memory cell and the second electrical signal to the OTP memory cell based on the control signal, and a sense amplifier configured to detect a first input signal applied from the normal memory cell based on the first electrical signal and detect a second input signal applied from the OTP memory cell based on the second electrical signal.

Provided is a memory device configured to control such that a first electrical signal is applied to the normal memory cell during a read operation of the normal memory cell and a second electrical signal having a magnitude greater than that of the first electrical signal is applied to the OTP memory cell during a read operation of the OTP memory cell, a read driver configured to provide the first electrical signal to the normal memory cell and the second electrical signal to the OTP memory cell based on the control signal, and a sense amplifier configured to detect a first input signal applied from the normal memory cell based on the first electrical signal and detect a second input signal applied from the OTP memory cell based on the second electrical signal.

A memory device includes a memory cell array that includes a first input/output unit and a second input/output unit, each of the first input/output unit and the second input/output unit including a first region including a plurality of memory cells and a second region including dummy memory cells, a first sensing circuit that determines data stored in the memory cells of the first input/output unit based on a first reference resistance, a second sensing circuit that determines data stored in the memory cells of the second input/output unit based on a second reference resistance, and a control logic circuit that controls a value of the first reference resistance and a value of the second reference resistance. The value of the first reference resistance and the value of the second reference resistance are different from each other.

A memory device includes a memory cell array that includes a first input/output unit and a second input/output unit, each of the first input/output unit and the second input/output unit including a first region including a plurality of memory cells and a second region including dummy memory cells, a first sensing circuit that determines data stored in the memory cells of the first input/output unit based on a first reference resistance, a second sensing circuit that determines data stored in the memory cells of the second input/output unit based on a second reference resistance, and a control logic circuit that controls a value of the first reference resistance and a value of the second reference resistance. The value of the first reference resistance and the value of the second reference resistance are different from each other.

A memory device is provided. The memory device includes a nonvolatile memory including a memory cell array, and a controller configured to control the nonvolatile memory. The memory cell array includes: a memory cell including a first magnetic tunnel junction element, an OTP (One-Time-Programmable) cell including a second magnetic tunnel junction element, and a reference cell connected to a first reference resistor for reading data for the memory cell or a second reference resistor for reading data from the OTP cell, wherein the controller is configured to set the second reference resistance, based on a first edge resistance value detected from a resistance distribution of OTP cells comprising the OTP cell or based on the first reference resistance.

A memory device is provided. The memory device includes a nonvolatile memory including a memory cell array, and a controller configured to control the nonvolatile memory. The memory cell array includes: a memory cell including a first magnetic tunnel junction element, an OTP (One-Time-Programmable) cell including a second magnetic tunnel junction element, and a reference cell connected to a first reference resistor for reading data for the memory cell or a second reference resistor for reading data from the OTP cell, wherein the controller is configured to set the second reference resistance, based on a first edge resistance value detected from a resistance distribution of OTP cells comprising the OTP cell or based on the first reference resistance.

A memory device may include a memory cell array, a write driver, and a sensing circuit. The memory cell array may include a normal cell connected to a bit line and a one time programmable (OTP) cell connected to the bit line. A program state of the normal cell may be determined by a first reference resistance and a program state of the OTP cell may be determined by a second reference resistance smaller than the first reference resistance. The write driver may perform a first OTP write operation on the OTP cell, and a sensing circuit may determine whether the first OTP write operation on the OTP cell is passed. The write driver may perform a second OTP write operation on the OTP cell experiencing a failure of the first OTP write operation.

A memory device may include a memory cell array, a write driver, and a sensing circuit. The memory cell array may include a normal cell connected to a bit line and a one time programmable (OTP) cell connected to the bit line. A program state of the normal cell may be determined by a first reference resistance and a program state of the OTP cell may be determined by a second reference resistance smaller than the first reference resistance. The write driver may perform a first OTP write operation on the OTP cell, and a sensing circuit may determine whether the first OTP write operation on the OTP cell is passed. The write driver may perform a second OTP write operation on the OTP cell experiencing a failure of the first OTP write operation.