A memory system includes a memory array comprising a plurality of memory cells. Each of the memory cells includes a transistor coupled to a first capacitor and a second capacitor in series, respectively. The memory system includes an authentication circuit operatively coupled to the memory array. The authentication circuit is configured to generate a Physically Unclonable Function (PUF) signature based on respective logic states of the plurality of memory cells, and wherein the logic state of each of the plurality of memory cells is determined based on a preceding breakdown of either the corresponding first capacitor or second capacitor.