A memory device is provided. The memory device includes a first transistor and a second transistor connected in series with the first transistor. The second transistor is programmable between a first state and a second state. A bit line connected to the second transistor. A sense amplifier connected to the bit line. The sense amplifier is operative to sense data from the bit line. A feedback circuit connected to the sense amplifier, wherein the feedback circuit is operative to control a bit line current of the bit-line.

An apparatus that includes a MOS transistor arranged in a well region supplied with a well potential, a temperature sensor configured to generate a control code indicating an ambient temperature, and a voltage generator configured to perform a control operation controlling a level of the well potential responsive to the control code in a first condition and perform a second control operation controlling a level of the well potential regardless of the control code in a second condition.

A liquid discharge head having an element board including an element configured to discharge a liquid includes a first storage element and a second storage element. The first storage element is a fuse element or an anti-fuse element. The second storage element is a semiconductor memory capable of holding a larger capacity than the first storage element. The second storage element is provided on an area other than the element board.

According to an embodiment, a storage device includes a plurality of storage elements, a plurality of readout circuits, and a delay circuit. The readout circuits include a first readout circuit and a second readout circuit different from the first readout circuit. The readout circuits each determines data stored in a corresponding one of the storage elements and outputs a result of the determination, in response to receipt of an activation signal. The delay circuit is connected at a first end to the first readout circuit and connected at a second end to the second readout circuit. The delay circuit supplies the activation signal to the second readout circuit with a time interval after supplying the activation signal to the first readout circuit.

According to an embodiment, a storage device includes a plurality of storage elements, a plurality of readout circuits, and a delay circuit. The readout circuits include a first readout circuit and a second readout circuit different from the first readout circuit. The readout circuits each determines data stored in a corresponding one of the storage elements and outputs a result of the determination, in response to receipt of an activation signal. The delay circuit is connected at a first end to the first readout circuit and connected at a second end to the second readout circuit. The delay circuit supplies the activation signal to the second readout circuit with a time interval after supplying the activation signal to the first readout circuit.

The present application discloses an OTP memory. A cell structure includes a first active region and a second active region that intersect vertically; an EDNMOS is formed in the first active region, and a PMOS is formed in the second active region; a body portion of a channel region of the PMOS is formed a drift region of the EDNMOS, a first polysilicon gate of the EDNMOS serves as a control gate, and a second polysilicon gate of the PMOS serves as a floating gate; and the PMOS is programmed by means of hot carriers generated in the drift region of the EDNMOS. The present application further discloses a method for manufacturing an OTP memory. In the present application, high-speed writing can be implemented.

An electronic system such as an imaging system may include processing circuitry and memory circuitry. The memory circuitry may include one-time-programmable memory having error correction code functionalities (e.g., SECDED functionalities). The one-time-programmable memory may have a first set of previously programmed bits and a second set of unprogrammed and unused bits. The processing circuitry may process instructions to update a bit in the second set of bits. To preserve the ECC functionalities (e.g., the ECC check bits associated with the first and second sets of bits, the processing circuitry may also update additional bits in the second set of bits.

An electronic system such as an imaging system may include processing circuitry and memory circuitry. The memory circuitry may include one-time-programmable memory having error correction code functionalities (e.g., SECDED functionalities). The one-time-programmable memory may have a first set of previously programmed bits and a second set of unprogrammed and unused bits. The processing circuitry may process instructions to update a bit in the second set of bits. To preserve the ECC functionalities (e.g., the ECC check bits associated with the first and second sets of bits, the processing circuitry may also update additional bits in the second set of bits.

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as read-only memory by not implementing erase or write commands. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to compare an address of a received command to the one or more addresses, and at least in part based on the comparison, determine not to implement the received command. The circuitry can be further configured to return an error message after determining not to implement the received command.

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as read-only memory by not implementing erase or write commands. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to compare an address of a received command to the one or more addresses, and at least in part based on the comparison, determine not to implement the received command. The circuitry can be further configured to return an error message after determining not to implement the received command.