The present invention is related to a clock generating device for generating an internal clock signal having a frequency correlated with a clock frequency of an external oscillator when the clock frequency of the external oscillator is not specified in advance. A clock generating device 105 comprises a memory 134 and a PLL circuit 120. The memory 134 is configured to store information about a frequency of an external clock signal generated by an external oscillator 200 at a predetermined timing. The PLL circuit 120 generates a second clock signal correlated with a first clock signal based on the information stored in the memory 134.

The present invention is related to a clock generating device for generating an internal clock signal having a frequency correlated with a clock frequency of an external oscillator when the clock frequency of the external oscillator is not specified in advance. A clock generating device 105 comprises a memory 134 and a PLL circuit 120. The memory 134 is configured to store information about a frequency of an external clock signal generated by an external oscillator 200 at a predetermined timing. The PLL circuit 120 generates a second clock signal correlated with a first clock signal based on the information stored in the memory 134.

A high-reliability one-time programmable memory adopting series high voltage partition, which relates to integrated circuit technology and comprises a first MOS tube, a second MOS tube and an anti-fuse element, wherein a gate end of the first MOS tube is connected to a second connecting line (WS), a first connecting end of the first MOS tube is connected to a gate end of the second MOS tube and a voltage limiting device, and a second connecting end of the first MOS tube is connected to a third connecting line (BL); a first connecting end of the second. MOS tube is connected to a fourth connecting line (BR), a second connecting end of the second MOS tube is connected to the third connecting line (BL), and a gate end of the second MOS tube is connected to the voltage limiting device and the second connecting end of the first MOS tube.

An apparatus comprises a plurality of memory cells in rows and columns, a first word line electrically coupled to a first group of memory cells through a first word line strap structure comprising a first gate contact, a first-level via, a first metal line and a second-level via and a second word line electrically coupled to a second group of memory cells through a second word line strap structure, wherein the second word line strap structure and the first word line strap structure are separated by at least two memory cells.

An apparatus comprises a plurality of memory cells in rows and columns, a first word line electrically coupled to a first group of memory cells through a first word line strap structure comprising a first gate contact, a first-level via, a first metal line and a second-level via and a second word line electrically coupled to a second group of memory cells through a second word line strap structure, wherein the second word line strap structure and the first word line strap structure are separated by at least two memory cells.

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as read-only memory by not implementing erase or write commands. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to compare an address of a received command to the one or more addresses, and at least in part based on the comparison, determine not to implement the received command. The circuitry can be further configured to return an error message after determining not to implement the received command.

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as read-only memory by not implementing erase or write commands. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to compare an address of a received command to the one or more addresses, and at least in part based on the comparison, determine not to implement the received command. The circuitry can be further configured to return an error message after determining not to implement the received command.

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as read-only memory by not implementing erase or write commands. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to compare an address of a received command to the one or more addresses, and at least in part based on the comparison, determine not to implement the received command. The circuitry can be further configured to return an error message after determining not to implement the received command.

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as read-only memory by not implementing erase or write commands. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to compare an address of a received command to the one or more addresses, and at least in part based on the comparison, determine not to implement the received command. The circuitry can be further configured to return an error message after determining not to implement the received command.

An integrated circuit (IC) chip embodiment includes first and second ROM cells arranged in a same row of a ROM array. The first and second ROM cells include first portions of first and second gate structures, respectively. The IC chip further includes a strap cell disposed between the first and second ROM cells. The strap cell includes second portions of the first and second gate structures. The first gate structure is physically separated from the second gate structure.