A memory device, includes: a memory array comprising a plurality of bit cells arranged along a plurality of rows and along a plurality of columns, respectively; and a control logic circuit coupled to the memory array, and configured to determine respective locations of a first plurality of diagonal bit cells of the memory array for testing one or more peripheral circuits coupled to the memory array, wherein the control logic circuit is further configured to determine respective locations of at least a second plurality of diagonal bit cells of the memory array for testing the one or more peripheral circuits, wherein a number of the plurality of rows is different than a number of the plurality of columns and the first plurality of diagonal bit cells span a first equal number of rows and columns and the second plurality of diagonal bit cells also span a second equal number of rows and columns.

The present invention relates to a single-layer polysilicon nonvolatile memory cell, a group structure thereof and a memory including the same. The memory cell includes a selection transistor and a storage transistor, wherein the selection transistor is connected in series with the storage transistor; and the selection transistor and the storage transistor are arranged on a substrate in a mutually perpendicular manner. A memory cell group includes four memory cells, arranged in a center-symmetrical array of two rowstwo columns. The memory comprises at least one memory cell group. The memory cell and the memory thereof are used as a one-time programming memory cell and memory, and have the advantages of small area, high programming efficiency and capability, and strong data retention capability.

The present invention relates to a single-layer polysilicon nonvolatile memory cell, a group structure thereof and a memory including the same. The memory cell includes a selection transistor and a storage transistor, wherein the selection transistor is connected in series with the storage transistor; and the selection transistor and the storage transistor are arranged on a substrate in a mutually perpendicular manner. A memory cell group includes four memory cells, arranged in a center-symmetrical array of two rowstwo columns. The memory comprises at least one memory cell group. The memory cell and the memory thereof are used as a one-time programming memory cell and memory, and have the advantages of small area, high programming efficiency and capability, and strong data retention capability.

A chip set for a terminal comprises at least one secure processor, in which a one-time programmable memory is integrated. At least one terminal serial number of the terminal is stored in the chip set. Information for securing the terminal serial number against tampering is stored in the one-time programmable memory.

A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.

One illustrative MRAM device disclosed herein includes a first bit cell and a second bit cell. The first bit cell comprises a first access transistor and a first MTJ stack. The first MTJ stack comprises a first pinned layer and a first free layer, wherein the first pinned layer is connected to the first access transistor. The second bit cell comprises a second access transistor and a second MTJ stack. The second MTJ stack comprises a second pinned layer and a second free layer, wherein the second free layer is connected to the second access transistor.

A state detection circuit for an anti-fuse memory cell includes: amplifier, having first input terminal connected with first reference voltage, second input terminal connected with first node and output terminal connected with second node; anti-fuse memory cell array, including anti-fuse memory cell sub-arrays, bit lines of sub-arrays are connected with first node, word lines of sub-arrays are connected with controller and each sub-array includes anti-fuse memory cells; first switch element, having first terminal connected with power supply, second terminal connected with first node and control terminal connected with second node; second switch element, having first terminal connected with power supply, second terminal connected with third node and control terminal connected with second node; third switch element, having first terminal connected with third node, grounded second terminal and control terminal connected with controller; and comparator, having first and second input terminals connected with third node and second reference voltage respectively.

In a method of forming a one-time-programming (OTP) bit, a thin-film memory device is provided, which includes at least one memory element and a transistor, and the memory element is coupled to the transistor in series. Then, an alternating current is applied to the memory element and the transistor, the power applied to the memory element is constrained, and the transistor is turned on to change the resistance of the memory element for a plurality of cycles of the alternating current until the resistance of the memory element is irreversibly changed.

A programmable resistive memory element and a method of adjusting a resistance of a programmable resistive memory element are provided. The programmable resistive memory element includes at least one resistive memory element. Each resistive memory element includes an Indium-Gallium-Zinc-Oxide (IGZO) resistive layer, a first electrical contact and a second electrical contact. The first and second electrical contacts are disposed on the IGZO resistive layer in the same plane. The programmable resistive memory element includes a voltage generator coupled to the first and second electrical contacts, constructed and arranged to apply a thermal treatment to the resistive memory element to adjust a resistance of the resistive memory element.

An integrated circuit (IC) device configured for multiple return material authorizations (RMAs) is provided. The IC device includes an asset and a return material authorization (RMA) counter fuse including a first fuse, a second fuse, and a third fuse. The IC device enters an RMA state in response to blowing the first fuse, a second state in response to blowing the second fuse, and the RMA state in response to blowing the third fuse.