A bi-sided pattern processor comprises a plurality of storage-processing units (SPU's). Each of the SPU's comprises at least a memory array and a pattern-processing circuit. The preferred pattern processor further comprises a semiconductor substrate with opposing first and second surfaces. The memory array is disposed on the first surface, whereas the pattern-processing circuit is disposed on the second surface. The memory array stores patterns; the pattern-processing circuit processes these patterns; and, they are communicatively coupled by a plurality of inter-surface connections.

A magnetoresistive random access memory (MRAM) includes an MRAM array having MRAM cells, each including a Magnetic Tunnel Junction (MTJ). The MRAM includes data write circuitry configured to write in one-time-programmable (OTP) write mode or in a non-OTP write mode. In the OTP write mode, the data write circuitry is configured to provide a high write voltage magnitude across selected MRAM cells of a first plurality of MRAM cells so as to permanently blow the corresponding tunnel dielectric layers of the selected MRAM cells. In the non-OTP write mode, the data write circuitry is configured to provide a lower write voltage magnitude across selected MRAM cells so as to set a magnetization of the corresponding free layer of each MRAM cell to modulate a resistance of each MRAM cell, without blowing the corresponding tunnel dielectric layer of each MRAM cell.

A magnetoresistive random access memory (MRAM) includes an MRAM array having MRAM cells, each including a Magnetic Tunnel Junction (MTJ). The MRAM includes data write circuitry configured to write in one-time-programmable (OTP) write mode or in a non-OTP write mode. In the OTP write mode, the data write circuitry is configured to provide a high write voltage magnitude across selected MRAM cells of a first plurality of MRAM cells so as to permanently blow the corresponding tunnel dielectric layers of the selected MRAM cells. In the non-OTP write mode, the data write circuitry is configured to provide a lower write voltage magnitude across selected MRAM cells so as to set a magnetization of the corresponding free layer of each MRAM cell to modulate a resistance of each MRAM cell, without blowing the corresponding tunnel dielectric layer of each MRAM cell.

Provided is an initialization control unit that causes a resistance value of a variable resistive element in an access restriction region to be changed to an initial value larger than a predetermined value. The resistance value is changed in a read only mode among the read only mode in which writing to the access restriction region is prohibited and a writable mode in which the writing to the access restriction region is permitted. The access restriction region is in a memory cell array in which the variable resistive elements are arranged, and the initialization control unit transitions to the writable mode. In addition, a write control unit causes a resistance value of an element corresponding to write data among the variable resistive elements in the access restriction region to be changed to a value smaller than the initial value in the writable mode, and transitions to the read only mode.

Provided is an initialization control unit that causes a resistance value of a variable resistive element in an access restriction region to be changed to an initial value larger than a predetermined value. The resistance value is changed in a read only mode among the read only mode in which writing to the access restriction region is prohibited and a writable mode in which the writing to the access restriction region is permitted. The access restriction region is in a memory cell array in which the variable resistive elements are arranged, and the initialization control unit transitions to the writable mode. In addition, a write control unit causes a resistance value of an element corresponding to write data among the variable resistive elements in the access restriction region to be changed to a value smaller than the initial value in the writable mode, and transitions to the read only mode.

A memory device, includes: a memory array comprising a plurality of bit cells arranged along a plurality of rows and along a plurality of columns, respectively; and a control logic circuit coupled to the memory array, and configured to determine respective locations of a first plurality of diagonal bit cells of the memory array for testing one or more peripheral circuits coupled to the memory array, wherein the control logic circuit is further configured to determine respective locations of at least a second plurality of diagonal bit cells of the memory array for testing the one or more peripheral circuits, wherein a number of the plurality of rows is different than a number of the plurality of columns and the first plurality of diagonal bit cells span a first equal number of rows and columns and the second plurality of diagonal bit cells also span a second equal number of rows and columns.

A device, including: an unsecure non-volatile memory; a secure device including: a processor; and a secure non-volatile memory; wherein the secure device is configured to: calculate a TMC value from an offset and a base value; store a TMC version value in the secure non-volatile memory and the insecure non-volatile memory, wherein the TMC version value is updated when TMC value is incremented the first time after the secure device is powered up; store the base value in the unsecure non-volatile memory; store the offset value in the unsecure non-volatile memory when the secure device is in a system power down state; store the offset value in the secure non-volatile memory when the secure device is in a rescue state; and store a TMC link value in the unsecure memory, wherein the TMC link value is based upon the base value and TMC version value stored in the unsecure memory.

A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.

Devices and methods for forming a device are presented. The device includes a substrate having a device region and first and second isolation regions surrounding the device region. The device includes a multi-time programmable (MTP) memory cell having a single transistor disposed on the device region. The transistor includes a gate having a gate electrode over a gate dielectric which includes a programmable resistive layer. The gate dielectric is disposed over a channel region having first and second sub-regions in the substrate. The gate dielectric disposed above the first and second sub-regions has different characteristics such that when the memory cell is programmed, a portion of the programmable resistive layer above one of the first or second sub-region is more susceptible for programming relative to portion of the programmable resistive above the other first or second sub-region.

Devices and methods for forming a device are presented. The device includes a substrate having a device region and first and second isolation regions surrounding the device region. The device includes a multi-time programmable (MTP) memory cell having a single transistor disposed on the device region. The transistor includes a gate having a gate electrode over a gate dielectric which includes a programmable resistive layer. The gate dielectric is disposed over a channel region having first and second sub-regions in the substrate. The gate dielectric disposed above the first and second sub-regions has different characteristics such that when the memory cell is programmed, a portion of the programmable resistive layer above one of the first or second sub-region is more susceptible for programming relative to portion of the programmable resistive above the other first or second sub-region.