A display panel and a display device are provided. The display panel includes: a display region and a peripheral region surrounding the display region. The display region comprises a first display sub-region and a second display sub-region. The width-to-length ratio of a channel region of an output transistor in a second gate shift register corresponding to the second display sub-region is decreased so as to reduce the charging time of pixels in the second display sub-region, so that the brightness of the pixels in the second display sub-region is consistent with the brightness region of pixels in the first display sub-region. The configuration facilitates achieving a narrow bezel while improving the display uniformness of the display panel without changing the existing circuit structure and occupying the additional bezel area.

A display panel and a display device are provided. The display panel includes: a display region and a peripheral region surrounding the display region. The display region comprises a first display sub-region and a second display sub-region. The width-to-length ratio of a channel region of an output transistor in a second gate shift register corresponding to the second display sub-region is decreased so as to reduce the charging time of pixels in the second display sub-region, so that the brightness of the pixels in the second display sub-region is consistent with the brightness region of pixels in the first display sub-region. The configuration facilitates achieving a narrow bezel while improving the display uniformness of the display panel without changing the existing circuit structure and occupying the additional bezel area.

A shift register circuit includes a denoising control sub-circuit and a denoising sub-circuit. The denoting control sub-circuit is configured to generate an alternating voltage signal according to a voltage of a first voltage terminal and a signal of a second clock signal terminal in response to a signal of a first clock signal terminal, to rectify the alternating voltage signal and then to output a signal to a first denoising control node, so that the voltage of the first denoting control node is maintained to be a voltage that enables the denoising sub-circuit to be turned on. The denoting sub-circuit is configured to denoise a scan signal output terminal in response to a voltage of the first denoising control node being the voltage that enables the denoising sub-circuit to be turned on.

A shift register unit, a scanning drive circuit, a display substrate and a display device. The shift register unit includes an output end, a node control end, a first output node control circuit, a second node control circuit, a second output node control circuit and an output circuit, the second node control circuit is electrically connected to a first clock signal line, the node control end, the first output node and the second node; the first output node control circuit is electrically connected to the second node and the first output node and is configured to control a potential of the first output node; the second output node control circuit is electrically connected to the second node and the second output node; the output circuit is electrically connected to a first output node, a second output node, a first voltage line, a second voltage line and an output end.

A shift register unit, a scanning drive circuit, a display substrate and a display device. The shift register unit includes an output end, a node control end, a first output node control circuit, a second node control circuit, a second output node control circuit and an output circuit, the second node control circuit is electrically connected to a first clock signal line, the node control end, the first output node and the second node; the first output node control circuit is electrically connected to the second node and the first output node and is configured to control a potential of the first output node; the second output node control circuit is electrically connected to the second node and the second output node; the output circuit is electrically connected to a first output node, a second output node, a first voltage line, a second voltage line and an output end.

A display substrate includes a scanning driving circuit arranged on a base substrate. The scanning driving circuit includes a plurality of shift register units and a first voltage signal line extending in a first direction. At least one shift register unit includes an output capacitor and a first transistor, a first electrode thereof is coupled to the first voltage signal line, and a second electrode thereof is coupled to an electrode plate of the output capacitor. A maximum distance between an orthogonal projection of the first electrode/second electrode of the first transistor onto the base substrate and an orthogonal projection of the first voltage signal line/the electrode plate of the output capacitor onto the base substrate is smaller than a first/second predetermined distance in a second direction, and the first direction intersects the second direction.

A display substrate includes a scanning driving circuit arranged on a base substrate. The scanning driving circuit includes a plurality of shift register units and a first voltage signal line extending in a first direction. At least one shift register unit includes an output capacitor and a first transistor, a first electrode thereof is coupled to the first voltage signal line, and a second electrode thereof is coupled to an electrode plate of the output capacitor. A maximum distance between an orthogonal projection of the first electrode/second electrode of the first transistor onto the base substrate and an orthogonal projection of the first voltage signal line/the electrode plate of the output capacitor onto the base substrate is smaller than a first/second predetermined distance in a second direction, and the first direction intersects the second direction.

A gate driving circuit and a display panel are provided. The gate driving circuit includes a plurality of shift register units as cascaded, and the plurality of shift register units as cascaded includes a first shift register unit including a first clock signal terminal, an (n+1)-th shift register unit including an (n+1)-th clock signal terminal, a second shift register unit including a second clock signal terminal, and an (n+2)-th shift register unit including an (n+2)-th clock signal terminal. The gate driving circuit further includes a first clock signal line connected to the first clock signal terminal and the (n+1)-th clock signal terminal, and a second clock signal line connected to the second clock signal terminal and the (n+2)-th clock signal terminal.

A gate driving circuit and a display panel are provided. The gate driving circuit includes a plurality of shift register units as cascaded, and the plurality of shift register units as cascaded includes a first shift register unit including a first clock signal terminal, an (n+1)-th shift register unit including an (n+1)-th clock signal terminal, a second shift register unit including a second clock signal terminal, and an (n+2)-th shift register unit including an (n+2)-th clock signal terminal. The gate driving circuit further includes a first clock signal line connected to the first clock signal terminal and the (n+1)-th clock signal terminal, and a second clock signal line connected to the second clock signal terminal and the (n+2)-th clock signal terminal.

A display panel, a display device, and a drive method are provided. The display panel includes a plurality of sub-pixel units arranged in an array and a gate drive circuit, and the array includes N rows. The gate drive circuit includes a plurality of cascaded shift register units and N+1 output terminals arranged in sequence, each of the plurality of cascaded shift register units is configured to output a gate scan signal for driving at least two rows of sub-pixel units in the N rows of the array to work; pixel drive circuits of an (n)-th row of sub-pixel units are connected to an (n)-th output terminal of the gate drive circuit to receive the gate scan signal as a scan drive signal, and sensing circuits of the (n)-th row of sub-pixel units are connected to an (n+1)-th output terminal of the gate drive circuit.