A shift register is described. The shift register includes a plurality of cells and register space. The shift register includes circuitry having inputs to receive shifted data and outputs to transmit shifted data, wherein: i) circuitry of cells physically located between first and second logically ordered cells are configured to not perform any logical shift; ii) circuitry of cells coupled to receive shifted data transmitted by an immediately preceding logically ordered cell comprises circuitry for writing into local register space data received at an input assigned an amount of shift specified in a shift command being executed by the shift register, and, iii) circuitry of cells coupled to transmit shifted data to an immediately following logically ordered cell comprises circuitry to transmit data from an output assigned an incremented shift amount from a shift amount of an input that the data was received on.

A shift register is described. The shift register includes a plurality of cells and register space. The shift register includes circuitry having inputs to receive shifted data and outputs to transmit shifted data, wherein: i) circuitry of cells physically located between first and second logically ordered cells are configured to not perform any logical shift; ii) circuitry of cells coupled to receive shifted data transmitted by an immediately preceding logically ordered cell comprises circuitry for writing into local register space data received at an input assigned an amount of shift specified in a shift command being executed by the shift register, and, iii) circuitry of cells coupled to transmit shifted data to an immediately following logically ordered cell comprises circuitry to transmit data from an output assigned an incremented shift amount from a shift amount of an input that the data was received on.

In a method of using an ultrasonic sensor comprising a two-dimensional array of ultrasonic transducers, a plurality of ultrasonic signals are transmitted according to a beamforming pattern at a position of the two-dimensional array. The beamforming pattern focuses the plurality of ultrasonic signals to location above the two-dimensional array, wherein the beamforming pattern identifies ultrasonic transducers of the two-dimensional array that are activated during transmission of the ultrasonic signals, and wherein at least some ultrasonic transducers of the beamforming pattern are phase delayed with respect to other ultrasonic transducers of the beamforming pattern. At least one reflected ultrasonic signal is received at the position according to a receive pattern, wherein the receive pattern identifies at least one ultrasonic transducers of the two-dimensional array that is activated during the receiving. The transmitting and the receiving are repeated at a plurality of positions of the two-dimensional array.

In a method of using an ultrasonic sensor comprising a two-dimensional array of ultrasonic transducers, a plurality of ultrasonic signals are transmitted according to a beamforming pattern at a position of the two-dimensional array. The beamforming pattern focuses the plurality of ultrasonic signals to location above the two-dimensional array, wherein the beamforming pattern identifies ultrasonic transducers of the two-dimensional array that are activated during transmission of the ultrasonic signals, and wherein at least some ultrasonic transducers of the beamforming pattern are phase delayed with respect to other ultrasonic transducers of the beamforming pattern. At least one reflected ultrasonic signal is received at the position according to a receive pattern, wherein the receive pattern identifies at least one ultrasonic transducers of the two-dimensional array that is activated during the receiving. The transmitting and the receiving are repeated at a plurality of positions of the two-dimensional array.

An execution unit is described. The execution unit includes an arithmetic logic unit (ALU) circuit having a first input to receive a first value and a second input to receive a second value. The ALU circuit includes circuitry to determine an absolute value of the first value and to add the absolute value to the second value. The first input is coupled to a first data path having register space and an output of another ALU of the execution unit circuit as alternative sources of the first value. The second input is coupled to a second data path having the register space as a source for the second value.

An execution unit is described. The execution unit includes an arithmetic logic unit (ALU) circuit having a first input to receive a first value and a second input to receive a second value. The ALU circuit includes circuitry to determine an absolute value of the first value and to add the absolute value to the second value. The first input is coupled to a first data path having register space and an output of another ALU of the execution unit circuit as alternative sources of the first value. The second input is coupled to a second data path having the register space as a source for the second value.

The present invention is directed towards a tubular nanosized magnetic wire, wherein the nanosized magnetic wire comprises: a tubular magnetic shell surrounding a longitudinal axis of the wire, at least one region of the tubular magnetic shell is capable of providing a 360 magnetic domain wall, wherein the 360 magnetic domain wall is self-stabilizing and has a magnetization going from a parallel alignment to a perpendicular alignment and to a parallel alignment with regards to the wire axis. The present invention also provides a practical method capable of making a tubular nanosized magnetic wire with a self-stabilizing, 360 magnetic domain wall. The present invention also relates to the use of the tubular nanosized magnetic wire in a racetrack memory device.

A gate driving circuit includes a plurality of shift register circuits, where the shift register circuits are configured to drive a plurality of pixel rows. The gate driving circuit may be operated in a first mode and a second mode. When the gate driving circuit is operated in the first mode, the gate driving circuit is configured to drive, in a single frame, all pixel rows to be displayed. When the gate driving circuit is operated in the second mode, the gate driving circuit is configured to drive, in the single frame, some of the pixel rows to be displayed, and driven pixel rows of two adjacent frames are different.

A gate driving circuit includes a plurality of shift register circuits, where the shift register circuits are configured to drive a plurality of pixel rows. The gate driving circuit may be operated in a first mode and a second mode. When the gate driving circuit is operated in the first mode, the gate driving circuit is configured to drive, in a single frame, all pixel rows to be displayed. When the gate driving circuit is operated in the second mode, the gate driving circuit is configured to drive, in the single frame, some of the pixel rows to be displayed, and driven pixel rows of two adjacent frames are different.

In a method of using an ultrasonic sensor comprising a two-dimensional array of ultrasonic transducers, a plurality of ultrasonic signals are transmitted according to a beamforming pattern at a position of the two-dimensional array. The beamforming pattern focuses the plurality of ultrasonic signals to location above the two-dimensional array, wherein the beamforming pattern identifies ultrasonic transducers of the two-dimensional array that are activated during transmission of the ultrasonic signals, and wherein at least some ultrasonic transducers of the beamforming pattern are phase delayed with respect to other ultrasonic transducers of the beamforming pattern. At least one reflected ultrasonic signal is received at the position according to a receive pattern, wherein the receive pattern identifies at least one ultrasonic transducers of the two-dimensional array that is activated during the receiving. The transmitting and the receiving are repeated at a plurality of positions of the two-dimensional array.