An in-memory processing apparatus includes: a memory cell array comprising memory cell groups configured to generate current sums of column currents flowing through respective column lines in response to input signals input through row lines; voltage controlled delay circuits configured to output, in response to an input of a start signal at a first time point, stop signals at second time points delayed by delay times determined based on magnitudes of applied sampling voltages corresponding to the current sums; and a time-digital converter configured to perform time-digital conversion at the second time points.

A counter includes a sampling unit suitable for sampling a logic state of a least significant bit (LSB) during a counting hold section, the counting hold section is present between first and second ramp sections; and a toggling control unit suitable for, in response to a clock and a sampling signal outputted from the sampling unit, generating the LSB according to a first voltage level of a counting target signal during a second part of the first ramp section and generating the LSB according to a second voltage level of the counting target signal during a first part of the second ramp section.

A counter includes a sampling unit suitable for sampling a logic state of a least significant bit (LSB) during a counting hold section, the counting hold section is present between first and second ramp sections; and a toggling control unit suitable for, in response to a clock and a sampling signal outputted from the sampling unit, generating the LSB according to a first voltage level of a counting target signal during a second part of the first ramp section and generating the LSB according to a second voltage level of the counting target signal during a first part of the second ramp section.

An embodiment includes an analog-to-digital converter device. A device may include a first track and hold amplifier configured to receive an analog input signal. The device may also include a plurality of paths coupled to an output of the first track and hold amplifier. Each path of the plurality of paths includes a second track and hold amplifier coupled to the first track and hold amplifier, and a successive approximation register analog-to-digital converter coupled to an output of the second track and hold amplifier. The successive-approximation analog-to-digital converter may include heterojunction bipolar transistors, a comparator, R-2R DAC, and a SiGe BiCMOS quasi-CML SAR register and sequencer.

An analog-to-digital converter includes a sample hold circuit configured to receive an analog input signal based on an operating mode, the operating mode being one of at least two modes including a sample mode and a hold mode. The sample hold circuit includes a first transistor including a control terminal and a first terminal, the first transistor configured to receive a control signal via the control terminal and receive the analog input signal via the first terminal. The analog-to-digital converter further includes a bootstrap switch operationally connected to the control terminal and the first terminal of the first transistor, the bootstrap switch configured to form a first current path from a power source based on the analog input signal and a boosted voltage of the control terminal of the first transistor in the sample mode, the control terminal bing along the first current path in the sample mode.

An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch coupled to provide an input signal to be sampled, and a second switch coupled to the first switch and to a first capacitor. The S/H circuit further includes a third switch coupled to the second switch and to a second capacitor, and a fourth switch to selectively couple to ground a node between the first and second switches.

An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch coupled to provide an input signal to be sampled, and a second switch coupled to the first switch and to a first capacitor. The S/H circuit further includes a third switch coupled to the second switch and to a second capacitor, and a fourth switch to selectively couple to ground a node between the first and second switches.

Methods and systems are described for receiving a sampling signal, pre-charging a pair of output nodes prior to a sampling interval, initiating the sampling interval by enabling a current source according to a first transition of the received sampling signal, generating a differential output voltage at the pair of output nodes by discharging the pair of output nodes according to a differential input signal, the pair of output nodes discharged according to current drawn by the current source during the sampling interval, terminating the sampling interval by disabling the current source in response to a second transition of the received sampling signal, and inhibiting a recharge of the pair of output nodes for a hold time after termination of the sampling interval and prior to initiation of a subsequent sampling interval.

Methods and systems are described for receiving a sampling signal, pre-charging a pair of output nodes prior to a sampling interval, initiating the sampling interval by enabling a current source according to a first transition of the received sampling signal, generating a differential output voltage at the pair of output nodes by discharging the pair of output nodes according to a differential input signal, the pair of output nodes discharged according to current drawn by the current source during the sampling interval, terminating the sampling interval by disabling the current source in response to a second transition of the received sampling signal, and inhibiting a recharge of the pair of output nodes for a hold time after termination of the sampling interval and prior to initiation of a subsequent sampling interval.

The present embodiments provide an analog to digital converter, including a beam splitter, M photodetectors, M amplifier modules, and an encoder. Each output end of the beam splitter is corresponding to an input end of a photodetector, an output end of each photodetector is connected to an input end of an amplifier module, and an output end of each amplifier module is connected to an input end of the encoder. The beam splitter splits an inputted analog optical signal into M optical signals, outputs each optical signal to a corresponding photodetector to convert each optical signal into a current signal, inputs each current signal to a corresponding amplifier module to generate an output voltage, and outputs the output voltage to a corresponding input end of the encoder.